Technical research papers

DFT is an annual Symposium providing an open forum for presentations in the field of defect and fault tolerance in VLSI systems inclusive of emerging technologies. One of the unique features of this symposium is to combine new academic research with state-of-the-art industrial data, necessary ingredients for significant advances in this field. All aspects of design, manufacturing, test, reliability, and availability that are affected by defects during manufacturing and by faults during system operation are of interest.


The Program Committee cordially invites you to participate and submit your contribution to DFT 2014. The conference topics include, but are not limited to, the following:

  • Yield Analysis and Modeling
    Defect/Fault analysis and models; statistical yield modeling; critical area and metrics.
  • Testing Techniques
    Built-in self-test; delay fault modeling and diagnosis; testing for analog and mixed circuits; signal and clock integrity.
  • Error Detection, Correction, and Recovery
    Self-testing and self-checking solutions; error-control coding; fault masking and avoidance; recovery schemes, space/time redundancy; hw/sw techniques.
  • Dependability Analysis and Validation
    Fault injection techniques and environments; dependability characterization.
  • Defect and Fault Tolerance
    Reliable circuit/system synthesis; radiation hardened/tolerant processes & design; design space exploration for dependable systems, transient/soft faults and errors.
  • Design For Testability in IC Design
    FPGA, SoC, NoC, ASIC, microprocessors.
  • Repair, Restructuring and Reconfiguration
    Repairable logic; reconfigurable circuit design; DFT for on-line operation; self-healing.
  • Totally Fail-Safe Design for Critical Applications
    Methodologies and case study applications to automotive, railway, avionics, industrial control, biomedicine, space and smart power networks.
  • Emerging Technologies
    DFT techniques for CNTs, QCA, DNA, RTDs, SETs, molecular devices and self-assembly.
  • Hardware security
    Fault attacks, fault tolerance-based counter- measures, Scan-based attacks and countermeasures, hardware trojans, security vs reliability trade-offs, interaction between VLSI test, trust, and reliability.


Each submission will be reviewed by the Program Co-Chairs to ensure compliance with the format criteria. The Program Co-Chairs will reject submissions that are not in compliance or that are out of scope of the conference.
All submissions that meet the criteria and fit the scope of the conference will be reviewed by at least three members of the Technical Program Committee. Submissions will be evaluated on the basis of originality, soundness, importance of contribution, quality of presentation, and appropriate comparison to related work.
The Program Co-Chairs will make the final decisions about which submissions are accepted for presentation at the conference.

Paper Publication and Presenter Registration

Papers will be accepted for regular or poster presentation at the symposium. Proceedings will be published and included in the IEEE Digital Library. It is mandatory that authors of accepted presentations attend to present their work at the conference and also that each accepted paper is accompanied by at least one full conference registration fee payment (no student registration) before the authors' registration deadline for the manuscript to be included and published in the proceedings.

Best Student Paper Award

All papers with a student as both primary author and presenter will be taken into consideration for the 2014 Best Student Paper Award.

Important dates

SubmissionMay 9, 2014 May 23, 2014 EXTENDED
NotificationJune 20, 2014 June 30, 2014 POSTPONED
Camera readyAugust 1, 2014


Program co-chairs

For questions, please contact the conference program co-chairs:

Program committee

List of the technical program committee members.


Downloadable Call for Submissions Flyers pdf.