The symposium
DFT (International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems) is an annual Symposium providing an open forum for presentations in the field of defect and fault tolerance in VLSI systems inclusive of emerging technologies. One of the unique features of this symposium is to combine new academic research with state-of-the-art industrial data, necessary ingredients for significant advances in this field.
Where
In 2015 DFT will be hosted at the University of Massachusetts Amherst.
When
October 12-14, 2015.
Location
The symposium sessions will be held in room 163 at 1 Campus Center Way, Amherst.
Preliminary technical program
The program of the event is available here.
Special Issue/Session
Authors will have the opportunity to submit an extended version of their paper presented at the symposium for a Issue/Special Section scheduled to appear in the last issue of 2016 in IEEE Transaction on Emerging Topics in Computing. More details here.
Keynote Talks
The following keynote talks are planned for the event!
David Brooks, Oct. 12, Reliable System Design in the Era of Specialization
David Brooks is the Haley Family Professor of Computer Science in the Paulson School of Engineering and Applied Sciences at Harvard University. Prior to joining Harvard, he was a research staff member at IBM T.J. Watson Research Center. Prof. Brooks received his BS in Electrical Engineering at the University of Southern California and MA and PhD degrees in Electrical Engineering at Princeton University. His research interests include resilient and power-efficient computer hardware and software design for high-performance and embedded systems.
Abhijit Chatterjee, Oct. 13, Statistical Correlation Driven Testing, Process Diagnosis and Tuning: The Signature Testing Paradigm and Beyond
Abhijit Chatterjee is a professor in the School of Electrical and Computer Engineering at Georgia Tech and a Fellow of the IEEE. He received his Ph.D in electrical and computer engineering from the University of Illinois at Urbana-Champaign in 1990. Dr. Chatterjee received the NSF Research Initiation Award in 1993 and the NSF CAREER Award in 1995. He has received six Best Paper Awards and three Best Paper Award nominations. His work on self-healing chips was featured as one of General Electric抯 key technical achievements in 1992 and was cited by the Wall Street Journal. In 1995, he was named a Collaborating Partner in NASA抯 New Millennium project. In 1996, he received the Outstanding Faculty for Research Award from the Georgia Tech Packaging Research Center, and in 2000, he received the Outstanding Faculty for Technology Transfer Award, also given by the Packaging Research Center. In 2007, his group received the Margarida Jacome Award for work on VIZOR: Virtually Zero Margin Adaptive RF from the Berkeley Gigascale Research Center (GSRC).
Dr. Chatterjee has authored over 400 papers in refereed journals and meetings and has 21 patents. He is a co-founder of Ardext Technologies Inc., a mixed-signal test solutions company and served as chairman and chief scientist from 2000-2002. His research interests includeerror-resilient signal processing and control systems,mixed-signal/RF/multi-GHz design and test and adaptive real-time systems.He served as the chair of the VLSI Technical Interest Group at Georgia Tech from 2010-2012. He co-leads the Samsung Center of Excellence in High-Speed Design and Test established at Georgia Tech in 2011.
Rob Aitken, Oct. 14, Building a Resilient Internet of Things
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