Conference technical program

Tentative Technical Program

(L) Long Paper
(S) Short Paper
Best Paper Candidate

Monday September 19, 2016

08:00-08:30am Registration

08:30-08:45am Conference opening

08:45-09:45am Keynote Talk: "Memory Errors in Modern Systems"
                       Vilas Sridharan -- AMD Inc., USA
                       Abstract and bio are available here

09:45-10:25am Session 1 - Aging

F. Lombardi (Northeastern U.)

(L) BTI Aware Thermal Management for Reliable DVFS Designs

H. Chahal, V. Tenentes, D. Rossi, and B. Al-Hashimi (U. Southampton)

(S) Prognosis of NBTI Aging Using a Machine Learning Scheme

N. Karimi (Rutgers U.) and K. Huang (San Diego State U.)

(S) Experimental Study and Analysis of Soft and Permanent Errors in Digital Cameras

I. Koren1, G. Chapman2, R. Thomas2, R. Thomas2 and Z. Koren1 (1Univ. of Massachusetts, 2Simon Fraser University)

10:25-10:45am Coffee Break

10:45-11:45am Session 2 - Fault Tolerance in Latches & Approximate Computing

N. Karimi (Rutgers U.)

(L) A Highly Robust Double Node Upset Tolerant Latch

A. Watkins and S. Tragoudas (Southern Illinois University Carbondale)

(L) Applying Efficient Fault Tolerance to Enable the Preconditioned Conjugate Gradient Solver on Approximate Computing Hardware

A. Schöll, C. Braun and H.-J. Wunderlich (University of Stuttgart)

(S) Construction of A Soft Error (SEU) Hardened Latch with High Critical Charge

H. Ueno and K. Namba (Chiba Univ.)

(S) Design and Error Analysis of an Approximate Two-Dimensional Convolver

F. Lombardi (Northeastern U.), J. Han (U. Alberta) and K. Chen(Northeastern U.)

11:45am-01:30pm Lunch Break

01:30-02:40pm Session 3 - System-level Approaches

A. Kumar (Technische U. Dresden)

(L) Combined On-line Lifetime-Energy Optimization for Asymmetric Multicores

C. Bolchini1, M. Carminati1, T. Mitra2 and T. S. Muthukaruppan2 (1Politecnico di Milano, 2National U. Singapore)

(L) Effects of Online Fault Detection Mechanisms on Probabilistic Timing Analysis

C. Chen, J. Panerati and G. Beltrame (Ecole Polytechnique de Montreal)

(L) Bounding Error Detection Latency in Safety Critical Systems with Enhanced Execution Fingerprinting

M. Liu and B. Meyer (McGill U.)

(S) Guiding Genetic Algorithms Using Importance Measures for Reliable Design of Embedded Systems

H. Aliee1, S. Vitzethum1, M. Glaß1, J.Teich1 and E. Borgonovo2 (1FAU, 2Bocconi U.)

02:40-03:00pm Coffee Break

03:00-04:10pm Session 4 - Special Session on Fault-Tolerant Realtime Systems

G. Beltrame (Ecole Polytechnique de Montreal)

(L) Fault-tolerant Scheduling of Multicore Mixed-Criticality Systems under Permanent Failures

Z. Al-Bayati (McGill U.), B. H. Meyer (McGill U.) and H. Zeng (Virginia Tech)

(L) Cross-Layer Fault-Tolerant Design of Real-Time Systems

S. S. Sahoo (National U. Singapore), B. Veeravalli (National U. Singapore) and A. Kumar (Technische U. Dresden)

(L) Fault-Aware Sensitivity Analysis for Probabilistic Real-Time Systems

L. Santinelli,(ONERA), Z. Guo (UNC) and L. George (LIGM – ESIEE)

4:20-5:20pm DFT TPC meeting

5:00-6:30pm Reception

Tuesday September 20, 2016

08:00-08:30am Registration

08:30-09:30am Keynote Talk: "Security versus Test and Reliability: The Crossroads and Beyond"
                       Swarup Bhunia -- University of Florida, USA
                       Abstract and bio are available here

09:30-10:30am Session 5 - FPGA & CMOS Technologies

S. Ghosh (Pennsylvenia State U.)

(L) Low Cost Resilient Regular Expression Matching on FPGAs

M. Leipnitz, E. N. de Souza and G. Nazar (U. Federal do Rio Grande do Sul)

(L) In-Place LUT Polarity Inversion to Mitigate Soft Errors for FPGAs

J. Su, J.-Y. Lee and L. He (UCLA)

(S) Detecting Intermittent Resistive Faults in Digital CMOS Circuits

H. Ebrahimi, A. Rohani and H.G. Kerkhoff(U. Twente)

(S) Soft Error Vulnerability Assessment of the Real-Time Safety-Related ARM Cortex-R5 CPU

X. Iturbe, B. Venu and E. Ozer (ARM)

10:30-10:50am Coffee Break

10:50-11:40am Session 6 - Architecture-level Techniques

B. Meyer (McGill U.)

(L) Efficient Utilization of Hierarchical iJTAG Networks for Interrupts Management

A. Ibrahim (U. Twente) and H. Kerkhoff (U. Twente / CTIT-TDT)

(S) Error Recovery Through Partial Value Similarity

A. Eker and O. Ergin (TOBB U. Economics and Technology)

(S) In-field functional test programs development flow for embedded FPUs

R. Cantoro1, D. Piumatti1, P. Bernardi1, A. Sansonetti2 and S. De Luca2 (1Politecnico di Torino, 22STMicroelectronics)

(S) Design and characterization of a high-safety hardware/software module for the acquisition of Eurobalise telegram

F. Giuliani1, M. Ottavi2, G. Cardarilli2, M. Re2, R. Fazzolari2, L. Di Nunzio2, A. Bruno1 and F. Zuliani1 (1NEAT S.r.l., 2University of Rome "Tor Vergata")

11:40am- 01:30pm Lunch Break and Awards Announcement

01:30-02:30pm Session 7 - Fault tolernce in NoC and SoC

Q. Yu (U. New Hampshire)

(L) CoBRA: Low Cost Compensation of TSV failures in 3D-NoC

R. Salamat (UC Irvine), M. Ebrahimi(KTH), N. Bagherzadeh (UC Irvine) and F. Verbeek (Radboud U.)

(L) A New Approach to Deadlock-Free Fully Adaptive Routing for High-Performance Fault-Tolerant NoCs

A. Charif, N.-E. Zergainoh and M. Nicolaidis (TIMA Laboratory)

(S) An Adaptive Routing Algorithm to Improve Lifetime Reliability in NoCs Architecture

J. Alshraiedeh and A. Kodi (Ohio U.)

(S) A Novel method for validation of fault-tolerant complex SoCs using low energy proton beams

G. Furano1, M. Ottavi2, A.Menicucci3, S. Di Mascio1, T. Szewczyk1, L. Campajola4, F. Di Capua4 and A. Fabbri5 (1European Space Agency, 2U. Rome "Tor Vergata“, 3TUDelft, 4NaplesFederico II, 5INFN, Roma Tre Section)

02:30-02:50pm Coffee Break

02:50-04:20pm Session 8 - Special Session on The use of VLSI techniques for Securing ICs against Attacks

S. Kundu (U. Massachusetts Amherst)

(L) Reliable PUF Design Using Failure Patterns from Time-Controlled Power Gating

X. Xu and D. Holcomb (U. Massachusetts, Amherst)

(L) Side Channel Attacks on STTRAM and Low-Overhead Countermeasures

A. Iyengar1, S. Ghosh1, N. Rathi1 and H. Naeimi2 (1Pennsylvania State Univrsity, 2Intel)

(L) On Meta-Obfuscation of Physical Layouts to Conceal Design Characteristics

V. C. Patil, A. Vijayakumar and S. Kundu (U. Massachusetts Amherst)

(L) Can Flexible, Domain Specific Programmable Logic Prevent IP Theft?

X. Cui1, K. Wu2, S. Garg2 and R. Karri2 (1Chongqing U., 2NYU)

It is possible to download the flyer of the program here.