IEEE Int. Symposium on Defect and Fault Tolerance
 in VLSI and Nanotechnology Systems
 IEEE Int. Symposium on Defect and Fault Tolerance
 in VLSI and Nanotechnology Systems

Keynote and invited speeches

Erik Jan Marinissen (IMEC, BE)

Murphy Goes 3D

"Whatever can, will go wrong" is the famous quote attributed to Edward Murphy. It has given Murphy the status of patron saint of all test engineers, since it is Murphy's Law that keeps them in business.
Three-dimensional stacking of ICs has kept folks in both technology and design research busy for several years. This research has advanced to the point that virtually all semiconductor companies have now released or announced 3D-SIC products, or are developing such products in stealth mode. No wonder, because 3D-SICs hold the promise of heterogeneous integration, inter-die connections with increased performance at lower power dissipation, and increased yield and hence decreased product cost. However, all these benefits can only materialize if 3D-SICs can be properly tested for manufacturing defects. Recently, the test community has started to work on test solutions for these IC products, signaling that their high-volume market introduction is indeed imminent.
This talk gives an overview of 3D-SIC technologies, associated test challenges, and emerging solutions.


Peter Harrod (Arm, UK)

Functional Safety and Security: the Challenges in Developing IP for These Markets

As embedded processor technology becomes ever more pervasive in our lives, there are many challenges involved in developing systems that are sufficiently powerful, energy efficient and cost effective, while at the same time meeting stringent requirements for reliability, functional safety and security. Autonomous driving is just one application area where these challenges are very real. Random faults that arise due to defects in manufacture or that occur in the field need to be handled, as well as malicious faults caused by security attacks.
This talk will cover some ways in which these challenges are being tackled, from the perspective of an IP provider that is creating general purpose processors for many diverse applications. Innovations in architecture, microarchitecture, logic design, circuit design, device technology, DFT and DFM can all play a part in meeting these requirements and will be discussed in the talk. The talk will conclude with some thoughts about future challenges.

Prof. Krishnendu (Krish) Chakrabarty (Duke University, US)

Fault-Tolerant Microbiology-on-a-Chip: Defects, Testing, Fault Avoidance, and Error Recovery in Microfluidic Biochips

Microfluidics technology has been commercialized for biochemistry and microbiology procedures such as sample preparation, drug discovery, and point-of-care diagnostics. Microfluidic biochips (or "lab on a chip") are now poised for adoption in even more exciting areas in microbiology, ranging from quantitative gene expression to epigenetics and single-cell analysis. A potential showstopper in this advance is the problem of defects and the associated concerns of reliability and fault tolerance. In this talk, the speaker will first describe the various microfluidic biochips technologies membrane valves, digital microfluidics, and micro-electrode dot array (MEDA)that have been developed over the years, and which are in various stages of commercial exploitation. The speaker will then highlight specific defects spanning multiple energy domains (electrical, fluidic, mechanical, biochemical, etc.) that have been reported for fabricated devices. Following this part, the presentation will describe testing and fault tolerance solutions that can be used for locating defects, performing error recovery, and bypassing defects for reliable microbiology on a chip. This talk will be followed by a special session consisting of three in-depth presentations on fault tolerance for specific types of microfluidic biochips.

Prof. Ahmad-Reza Sadeghi (TU Darmstadt, DE)

Hardware-Assisted Security: Promises, Pitfalls and Opportunities

Emerging technologies such as the Internet of Things (IoT) involve large numbers of connected heterogeneous devices and pose a variety of security and privacy challenges on the underlying devices.
In this context, hardware security architectures and primitives play an important role and are being increasingly deployed in practice. Hardware-assisted security aims at providing trust anchors and trusted execution environments to protect IT systems, in particular to secure the insecure legacy software. Over the past two decades we have seen a number of hardware security technologies and trends from Trusted Platform Module (TPM), ARM's TrustZone, Physically Unclonable Functions (PUFs), to very recent advances such as Intel's Software Guard Extension (SGX).
In this talk we first discuss the real-world impact of currently deployed hardware-assisted security solutions and their strengths and shortcomings. Then we discuss some recent research directions and challenges in this field.