Final Program (download)
Wednesday September 26, 2007
7:30 – 9:00 Registration
9:00 – 9:20 Opening Session
9:20 – 10:40 Session 1 – Fault Injection and Reliability Analysis
Session Chair: Raoul Velazco (TIMA Laboratory)
“FLIPPER: A Flexible Platform for Evaluating Single Event Upset Mitigation Schemes for SRAM based FPGAs ”
Monica ALDERIGHI, Fabio CASINI, Sergio D'ANGELO, Marcello MANCINI, Giacomo SECHI (INAF), Sandro PASTORE (Sanitas EG), Roland WEIGAND (ESA/ESTEC)“A Functional Verification based Fault Injection Environment”
Alberto BOSIO (LIRMM), Stefano DI CARLO, Alfredo BENSO (Politecnico di Torino), Riccardo MARIANI (YOGITECH SpA)“Comparing fail-safe microcontroller architectures in light of IEC 61508”
Riccardo MARIANI (YOGITECH SpA), Peter FUHRMANN (Philips Research Europe)“A Framework for Reliability Assessment and Enhancement in Multi-Processor Systems-On-Chip”
Giovanni Beltrame (European Space Agency), Cristiana BOLCHINI, Antonio MIELE, Luca FOSSATI, Donatella SCIUTO (Politecnico di Milano)
Coffee break (10:40 – 11:00)
11:00 – 12:20 Session 2 – Single Event Effects
Session Chair: Hideo Hito (Chiba University)
“Estimating Error Propagation Probabilities with Bounded Variances”
Mehdi TAHOORI, Hossein ASADI (Northeastern University), Chandra Tirumurti (Intel Corporation)“A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction”
Sybille HELLEBRAND (University of Paderborn), Christian ZOELLIN (Universitaet Stuttgart), Hans-Joachim WUNDERLICH (Universität Stuttgart), Bernd STRAUBE (Fraunhofer Inst. für Int. Schaltungen), Thorsten COYM (Fraunhofer IIS-EAS Dresden), Stefan LUDWIG (Fraunhofer Paderborn)“Estimation of Electromigration-Aggravating Narrow Interconnects Using a Layout Sensitivity Model”
Rani Abou GHAIDA, Payman ZARKESH-HA (University of New Mexico)“SET emulation under a quantized delay model”
Mario GARCIA VALDERAS, Raul FERNANDEZ CARDENAL, Celia LOPEZ ONGIL, Marta PORTELA-GARCIA, Luis ENTRENA (Universidad Carlos III)
Lunch (12:20 – 13:30)
13:30 – 14:50 Session 3 – Reliable NoCs and SoCs
Session Chair: Donatella Sciuto (Politecnico di Milano)
“Reliable Network-on-Chip Using a Low Cost Unequal Error Protection Code”
Avijit DUTTA, Nur TOUBA (University of Texas at Austin)“Fault Tolerant Source Routing for Network-on-chip”
Yong-Bin KIM, Young Bok KIM (Northeastern University)“Online NoC Switch Fault Detection and Diagnosis Using a High Level Fault Mode”
Armin ALAGHI, Naghmeh KARIMI, Mahshid SEDGHI (University of Tehran), Zainalabedin NAVABI (Northeastern University)“Fault Tolerant SoC Architecture Design for JPEG2000 using Partial Reconfigurability”
Abderrahim Doumar (University of Technology of Troyes), Kentaroh Katoh, Hideo Ito (Chiba University), Nawal Hamane (LeadTechDesign)
Coffee break (14:50 – 15:10)
15:10 – 16:10 Session 4 – Defect and Fault Tolerance
Session Chair: Luis Entrena (Universidad Carlos III)
“Sensitivity of TMR-hardened circuits to multiple SEUs induced by alpha particles in commercial SRAM-based FPGAs”
Andrea MANUZZATO, Paolo RECH, Simone GERARDIN, Alessandro PACCAGNELLA (University of Padova), Luca STERPONE, Massimo VIOLANTE (Politecnico di Torino)“TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs”
Cristiana BOLCHINI, Antonio MIELE, Marco D. SANTAMBROGIO (Politecnico di Milano)“Optimization of Self Checking FIR filters by means of Fault Injection Analysis”
Salvatore PONTARELLI (University of Rome Tor Vergata), Luca STERPONE (Politecnico di Torino), Gian Carlo CARDARILLI, Marco RE (University of Rome Tor Vergata), Matteo SONZA REORDA (Politecnico Di Torino), Adelio SALSANO (University of Rome Tor Vergata)
Short break (16:10 – 16: 20)
16:20 – 18:20 Interactive Poster Session
Session Chair: Salvatore Pontarelli (Universita' di Roma, “Tor Vergata”)
“A Defect-Tolerant Molecular-Based Memory Architecture”
Yoon-Hwa CHOI, Myeong-Hyeon LEE (Hongik University)“Checker Design for On-line Testing of Xilinx FPGA Communication”
Zdenek KOTASEK, Martin STRAKA, Jiri TOBOLA (Brno University of Technology)“Defect-Tolerant Gate Macro Mapping & Placement in Clock-Free Nanowire Crossbar Architecture”
Ravi BONAM (Univ. of Missouri-Rolla), Yong-Bin KIM (Northeastern Univ.), Minsu CHOI (Univ. of Missouri-Rolla)“Delay fault detection problems in circuits featuring a low combinational depth”
Michele FAVALLI (Univ. of Ferrara)“Empirical Analysis of the Dependence of Test Power, Delay, Energy and Fault Coverage on the Architecture of LFSR-Based TPGs”
Mehdi KAMAL (SRRF), Somayyeh KOOHI, Shaahin HESSABI (Sharif University of Technology)“Fault Tolerant Arithmetic Operations with Multiple Error Detection and Correction”
Mojtaba Valinataj, Saeed Safari (Univ. of Tehran)“Production Yield and Self-Configuration in the future Massively Defective Nanochips”
Piotr Zajac, Jacques Henri Collet (CNRS)“Test Generation for Single and Multiple Stuck-at Faults of a Combinational Circuit Designed by Covering Shared ROBDD with CLBs”
Anjela MATROSOVA, Ekaterina LOUKOVNIKOVA, Sergei OSTANIN, Alexandra ZINCHUCK, Ekaterina NIKOLAEVA (Tomsk State University)“Testing of Asynchronous NULL Conventional Logic (NCL) Circuits in Synchronous-Based Designs”
Waleed K. AL-ASSADI, Sindhu KAKARLA (Univ. of Missouri-Rolla)“Timing-Aware Diagnosis for Small Delay Defects”
Takashi AIKYO (Semiconductor Technology Academic Research Centor), Hiroshi TAKAHASHI, Yoshinobu HIGAMI, Junichi OOTSU, Kyohei ONO, Yuzo TAKAMATSU (Ehime University)
Thursday September 27, 2007
8:30 – 9:50 Session 5 – Testing and Design for Testability
Session Chair: Renato Stefanelli (Politecnico di Milano)
“A-Diagnosis: A Complement to Z-Diagnosis”
Irith POMERANZ (Purdue University), Sudhakar REDDY (University of Iowa)“Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines”
Hiroshi TAKAHASHI, Yoshinobu HIGAMI, Toru KIKKAWA, Takashi AIKYO, Yuzo TAKAMATSU (Ehime University), Koji YAMAZAKI, Toshiyuki TSUTSUMI (Meiji University), Hiroyuki YOTSUYANAGI, Masaki HASHIZUME (University of Tokushima)“Analysis of Specified Bit Handling Capability of Combinational Expander Networks”
Abhijit JAS, Srinivas PATIL (Intel Corporation)“Reduction of Fault Latency in Sequential Circuits by using Decomposition”
Ilya LEVIN, Benjamin ABRAMOV, Vladimir OSTROVSKY (Tel Aviv University)
Coffee break (9:50 – 10:10)
10:10 – 11:10 Session 6 – Soft Errors
Session Chair: Regis Leveugle (TIMA Laboratory)
“Soft Error Hardening for Asynchronous Circuits”
Weidong KUANG, Casto Manuel IBARRA (University of Texas – Pan American), Peiyi ZHAO (Chapman University)“Soft Error Hardened Latch Scheme for Enhanced Scan Based Delay Fault Testing”
Takashi IKEDA, Kazuteru NAMBA, Hideo ITO (CHIBA University)“An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains”
Edgar E. SANCHEZ SANCHEZ (Politecnico di Torino), Davide APPELLO (STMicroelectronics), Matteo SONZA REORDA, Paolo BERNARDI, Michelangelo GROSSO (Politecnico di Torino), Jorge Luis LAGOS-BENITES (Pontificia Universidad Católica del Perú), Danilo RAVOTTO (Politecnico di Torino)
Short break (11:10 – 11:30)
11:30 – 12:30 Session 7 – Defect and Fault Tolerance
Session Chair: Dimitri Gizopoulos (University of Piraeus)
“Improving the Tolerance of Pipeline Based Circuits to Power Supply or Temperature Variations”
Jorge SEMIAO (Escola Superior de Tecnologia - Universidade do Algarve), Juan J. RODRIGUEZ-ANDINA (University of Vigo), Fabian VARGAS (Catholic University - PUCRS), Marcelino BICHO DOS SANTOS (IST/INESC-ID), Isabel TEIXEIRA (INESC-ID), Joao Paulo TEIXEIRA (IST, Lisboa Technical University)“RAM-based Fault Tolerant state machines for FPGAs”
Laura FRIGERIO, Fabio SALICE (Politecnico di Milano)“Spare Parts in Analog Circuits: a Filter Example”
Erik SCHULER, Adão DE SOUZA JUNIOR, Luigi CARRO (Universidade Federal do Rio Grande do Sul)
Lunch (12:30 – 13:40)
13:40 – 14:40 Session 8 – Dependable solutions for Memories and Storage
Session Chair: Israel Koren (University of Massachusetts)
“A Sharable Built-in Self-repair for Semiconductor Memories with 2-D Redundancy Scheme”
Swapnil BAHL (STMicroelectronics)“Matrix Codes: Multiple Bit Upsets Tolerant Method for SRAM Memories”
Costas Argyrides, Hamid R. Zarandi, Dhiraj K. Pradhan (Bristol University)“Reconstruction of Erasure Correcting Codes for Dependable Distributed Storage System without Spare Disks”
Haruhiko KANEKO, Eiji FUJIWARA (Tokyo Institute of Technology)
Short break (14:40 – 14:50)
14:50 – 15:50 Session 9 – Reliable Design Techniques
Session Chair: Fabrizio Lombardi (Northeastern University)
“Lazy Error Detection for Microprocessor Functional Units”
Mahmut YILMAZ, Albert MEIXNER, Sule OZEV, DANIEL SORIN (Duke University)“Effective Checkpoint and Rollback Using Hardware/OS Collaboration”
Michele PORTOLAN (TIMA Laboratory), Regis LEVEUGLE (TIMA Laboratory)“On-Line Periodic Self-Testing of High-Speed Floating-Point Units in Microprocessors”
George XENOULIS, Mihalis PSARAKIS, Dimitris GIZOPOULOS, Antonis PASCHALIS (University of Athens)
Coffee break (15:50 – 16:10)
16:10 – 18:30 Panel:
“On-Chip Reliability Availability Serviceability (RAS) Design Costs: Can processors in consumer systems encroach in the high end space today?” Moderator: Prashant Joshi (Intel)
Friday September 28, 2007
8:30 – 9:30 Keynote Address: Rajesh Galivanche (Intel)
9:30 – 11:10 Session 10 – Emerging technologies – 1
Session Chair: Marco Ottavi (Advanced Micro Devices)
“A Scalable Framework for Defect Isolation of DNA Self-assembled Networks”
Masaru FUKUSHI, Susumu HORIGUCHI (Tohoku University), Luke DEMORACSKI, Fabrizio LOMBARDI (Northeastern University)“Error Tolerance of DNA Self-Healing Assemblies by Puncturing”
Masoud HASHEMPOUR, Zahra MASHREGHIAN ARANI, Fabrizio LOMBARDI (Northeastern University)“Fault Secure Encoding and Decoding for Nanotechnology Memory Architecture”
Helia NAEIMI (Caltech), Andre DEHON (University of Pennsylvania)“Safety Evaluation of NanoFabrics”
Michelangelo GROSSO, Maurizio REBAUDENGO, Matteo SONZA REORDA (Politecnico Di Torino)“Nanofabric PLA architecture with Redundancy Enhancement”
Waleed AL-ASSADI, Mandar JOSHI (University of Missouri-Rolla)
Coffee break (11:20 – 11:40)
11:40 – 12:40 Session 11 – Testing
Session Chair: Luigi Carro (Univ Federal Rio Grande do Sul)
“Hierarchical Fault Compatibility Identification for Test Generation with a Small Number of Specified Bits”
Stelios N. NEOPHYTOU, Maria MICHAEL (University of Cyprus)“High quality test vectors for bridging faults in the presence of IC's parameters variations”
Michele FAVALLI (University of Ferrara), Marcello DALPASSO (University of Padova)“Semi-Concurrent On-Line Testing of Transition Faults Through Output Response Comparison of Identical Circuits”
Irith POMERANZ (Purdue University), Sudhakar REDDY (University of Iowa)
Lunch (12:40 – 13:50)
13:50 – 14:50 Session 12 – Emerging technologies – 2
Session Chair: Maurizio Rebaudengo (Politecnico di Torino)
“Testing Reversible One-Dimensional QCA Arrays for Multiple Faults”
Jing HUANG, Xiaojun MA (Northeastern University), Cecilia METRA (University of Bologna), Fabrizio LOMBARDI (Northeastern University)“Probabilistic Analysis of a Molecular Quantum-Dot Cellular Automata Adder”
Timothy J DYSART, Peter KOGGE (University of Notre Dame)“On the Error Effects of Random Clock Shifts in Quantum-dot Cellular Automata Circuits”
Marco OTTAVI (NU/AMD), Hamid HASHEMPUOUR (LTX), Faizal KARIM (University of British Columbia), Vamsi VANKAMAMIDI (Northeastern University), Konrad WALUS (University of British Columbia), Andre IVANOV(University of British Columbia)
Short break (14:50 – 15:00)
15:00 – 16:20 Session 13 – Reliable Applications
Session Chair: Cecilia Metra (Universita' di Bologna)
“Evaluation of Register-Level Protection Techniques for the Advanced Encryption Standard by Multi-Level Fault Injections”
Paolo MAISTRI (TIMA Laboratory), Regis LEVEUGLE (TIMA Laboratory), Pierre VANHAUWAERT (TIMA Laboratory)“Power Attacks Resistance of Cryptographic S-boxes in presence of Error Detection Procedures”
Francesco REGAZZONI (ALaRI - University of Lugano), Thomas EISENBARTH (Ruhr Universitaet Bochum), JOHANN GROSZSCHAEDL (University of Bristol), Luca BREVEGLIERI (Politecnico di Milano), Paolo IENNE (EPFL), ISRAEL KOREN (University of Massachusetts), Christof PAAR (Horst Goertz Institute)“A Fault-Tolerant Active Pixel Sensor to Correct In-Field Hot Pixel Defects”
Jozsef DUDAS, Michelle LA HAYE, Jenny LEUNG, Glenn CHAPMAN (Simon Fraser University“Quantitative Analysis of In-Field Defects in Image Sensor Arrays”
Jenny LEUNG, Jozsef DUDAS, Glenn CHAPMAN (Simon Fraser University), Israel KOREN, Zahava KOREN (University of Massachusetts)
16:20 – 16:30 Closing Remarks