Call for papers

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DFT is an annual Symposium providing an open forum for presentations in the field of defect and fault tolerance in VLSI and nanotechnology systems inclusive of emerging technologies. One of the unique features of this symposium is to combine new academic research with state-of-the-art industrial data, necessary ingredients for significant advances in this field. All aspects of design, manufacturing, test, reliability, and availability that are affected by defects during manufacturing and by faults during system operation are of interest. Topics include (but are not limited to) the following:

1. Yield Analysis and Modeling
   Defect/fault analysis and models; statistical yield modeling; diagnosis; critical area and other metrics.
2. Testing Techniques
   Built-in self-test; delay fault modeling and diagnosis; testing for analog and mixed circuits; online testing; signal and clock integrity.
3. Design For Testability in IC Design
   FPGA, SoC, NoC, ASIC, low power design and microprocessors.
4. Error Detection, Correction, and Recovery
   Self-testing and self-checking solutions; error-control coding; fault masking and avoidance; recovery schemes, space/time redundancy; hw/sw techniques; architectural and system-level techniques.
5. Dependability Analysis and Validation
   Fault injection techniques and frameworks; dependability and characterization.
6. Repair, Restructuring and Reconfiguration
   Repairable logic; reconfigurable circuit design; DFT for on-line operation; self-healing; reliable FPGA-based systems.
7. Radiation effects
   SEEs on nanotechnologies; modeling of radiation environments; radiation experiments; radiation hardening techniques.
8. Defect and Fault Tolerance
   Reliable circuit/system synthesis; fault tolerant processes and design; design space exploration for dependable systems, transient/soft faults.
9. Aging and Lifetime Reliability
   Aging characterization and modeling; design and run-time reliability, thermal, and variability management and recovery.
10. Dependable Applications and Case Studies
    Methodologies and case studies for IoTs, automotive, railway, avionics and space, autonomous systems, industrial control, etc.
11. Emerging Technologies
    Techniques for 2.5D/3D ICs, quantum computing architectures, memristors, spintronics, microfluidics, etc.
12. Design for Security
    Fault attacks, fault tolerance-based countermeasures, scan-based attacks and countermeasures, hardware trojans, security vs. reliability trade-offs, interaction between VLSI test, trust, and reliability.

Paper Submission: authors are invited to submit original and unpublished contributions in the areas described above. Submitted papers should be no longer than 6 pages and adhere to the IEEE conference template, 2-columns style (available on conference web site). Papers can be accepted as regular papers (former oral presentations) or short papers (formerly posters). Both types of paper will be included in the IEEE proceedings; the page limit for proceedings is 6 pages for regular papers and 4 pages for short papers. Please refer to the symposium web page for updated information. All accepted papers will be considered as candidates for the DFT 2022 Best Paper Award.

Call for Special Sessions: Proposals for Special Sessions are also invited. For more information, visit symposium website and see the specific call.

Paper Publication: Only original, unpublished work will be accepted, for oral presentation at the symposium. Proceedings will be published by the IEEE Computer Society and will appear in the Digital Library.

Author Registration: Every accepted paper MUST have at least one full paid registration by the time the camera-ready paper is submitted for inclusion in the symposium proceedings, and one of the authors is expected to attend the Symposium and present the paper.

Microelectronics Reliability Special Issue: Papers presented within the symposium will be invited for a submission in extended version in a special issue/section of the Microelectronics Reliability journal.