Monday October 12, 2015

09:00-10:00 Registration

10:00-10:15 Conference opening

10:15-11:15 Keynote Talk: "Reliable System Design in the Era of Specialization"
                       David Brooks, Harvard University

Omer Khan, University of Connecticut

11:15-11:25 Short Break

11:25-12:25 Session 1 – Memories and Emerging Technologies

Salvatore Pontarelli, CNIT, Italy

1.1R Evaluating the Impact of Spike and Flicker Noise in Phase Change Memories

Salin Junsangsri, Fabrizio Lombardi, and Jie Han

1.2R A Fault Detection and Repair of DSC Arrays through Memristor Sensing

Jimson Mathew, Yuanfan Yang, Marco Ottavi, Thomas Brown, Andrea Zampetti, Aldo Di Carlo, Abusaleh M. Jabir and Dhiraj Pradhan

1.3S Asymmetric ECC Organization in 3D-Memory via Spare Column Utilization

Hyunseung Han and Joon-Sung Yang

1.4S Exploring Error-Tolerant Low-Power Multiple-output Read Scheme for Memristor-Based Memory Arrays

Adedotun Adeyemo, Jimson Mathew, Abusaleh Jabir and Dhiraj K Pradhan

12:30-01:50 Lunch Break

01:50-03:30 Session 2 - Best Paper Candidates

Fabrizio Lombardi, Northeastern University

2.1R RotR: Rotational Redundant Task Mapping for Fail-operational MPSoCs

Badrun Nahar and Brett H. Meyer

2.2R On Enhancing the Debug Architecture of a System-on-Chip (SoC) to Detect Software Attacks

Jerry Backer, David Hely and Ramesh Karri

2.3R Software-Based On-Chip Thermal Sensor Calibration for DVFS-enabled Many-core Systems

Sami Teräväinen, Mohammad-Hashem Haghbayan, Amir-Mohammad Rahmani, Pasi Liljeberg and Hannu Tenhunen

2.4R Single Event Upsets and Hot Pixels in Digital Imagers

Glenn H. Chapman, Rahul Thomas, Rohan Thomas, Klinsmann Joel Meneses, Tommy Yang, Israel Koren, and Zahava Koren

2.5R Accelerated Microarchitectural Fault Injection-Based Reliability Assessment

Manolis Kaliorakis, Sotiris Tselonis, Athanasios Chatzidimitriou and Dimitris Gizopoulos

03:30-04:00 Coffee Break

04:00-04:20 Invited Talk: "Achievements of the COST Action MEDIAN"
                       Marco Ottavi, University of Rome "Tor Vergata"

Maria K. Michael, University of Cyprus

04:20-05:40 Session 3 - Fault Tolerance

Israel Koren, University of Massachusetts

3.1R Hot Spare Components for Performance-Cost Improvement in Multi-core SIMT

Seyyed Hasan Mozafari and Brett H. Meyer

3.2R Low-Overhead Fault-Tolerance for the Preconditioned Conjugate Gradient Solver

Alexander Schoell, Claus Braun, Michael A. Kochte and Hans-Joachim Wunderlich

3.3R On-line Detection of Intermittent Faults in Digital-to-Analog Converters

Mani Soma

3.4S A Dual-Layer Fault Manager for Systems based on Xilinx Virtex FPGAs

Ignacio Herrera-Alzu, Marisa Lopez Vallejo and Carlos Gil-Soriano

3.5S REPAIR: Hard-Error Recovery via Re-Execution

Jyothish Soman, Negar Miralaei, Alan Mycroft and Timothy Jones

Tuesday October 13, 2015

08:00-08:30 Registration

08:30-09:30 Keynote Talk: "Statistical Correlation Driven Testing, Process Diagnosis and Tuning: The Signature Testing                        Paradigm and Beyond"
                       Abhijit Chatterjee, Georgia Tech

Sandip Kundu, University of Massachusetts

09:30-10:30 Session 4 – Soft Errors

Glenn Chapman, Simon Fraser University

4.1.R A Method to Protect Bloom Filters from Soft Errors

Pedro Reviriego, Salvatore Pontarelli, Juan Antonio Maestro and Marco Ottavi

4.2R Influence of triple-well technology on laser fault injection and laser sensor efficiency

Nicolas Borrel, Clement Champeix, Edith Kussener, Wenceslas Rahajandraibe, Mathieu Lisart, Alexandre Sarafianos and Jean-Max Dutertre

4.3R Using Value Similarity of Registers for Soft Error Mitigation

Abdulaziz Eker and Oguz Ergin

10:30-11:00 Coffee Break

11:00-12:30 Session 5 - Hardware Security

Qiaoyan Yu, University of New Hampshire

5.1R Security Analysis of Logic Encryption Against the Most Effective Side-Channel Attack: DPA

Muhammad Yasin, Bodhisatwa Mazumdar, Sk Subidh Ali and Ozgur Sinanoglu

5.2R Reliable Hash Trees for Post-quantum Stateless Cryptographic Hash-based Signatures

Mehran Mozaffari-Kermani and Reza Azarderakhsh

5.3R Chip-level Anti-reverse Engineering using Transformable Interconnects

Shuai Chen, Junlin Chen, Domenic Forte, Jia Di, Mark Tehranipoor and Lei Wang

5.4S Scan Attack on Elliptic Curve Cryptosystem

Sk Subidh Ali and Ozgur Sinanoglu

5.5S Enhancing Embedded SRAM Security and Error Tolerance with Hardware CRC and Obfuscation

Senwen Kan, Marco Ottavi and Jennifer Dworak

5.6S A BIST Approach for Counterfeit Circuit Detection based on NBTI Degradation

Puneet Savanur, Phaninder Alladi and Spyros Tragoudas

12:30-01:40 Lunch Break

01:40-03:00 Session 6 - Test Generation and Fault Simulation

Prashant Joshi, Cadence

6.1R Quest for a Quantum Search Algorithm for Testing Stuck-at Faults in Digital Circuits

Muralidharan Venkatasubramanian and Vishwani D. Agrawal

6.2R Piecewise-Functional Broadside Tests Based on Intersections of Reachable States

Irith Pomeranz

6.3R Predictive LBIST Model and Partial ATPG for Seed Extraction

Gustavo Contreras, Nisar Ahmed, Leroy Winemberg and Mark Tehranipoor

6.4S A CMOS ripple detector for integrated voltage regulator testing

Cagatay Ozmen, Aydin Dirican, Nurettin Tan, Hieu Nguyen and Martin Margala

6.5S Adaptive Fault Simulation on Many-core Microprocessor Systems

Mohammad-Hashem Haghbayan, Sami Teräväinen, Amir-Mohammad Rahmani, Pasi Liljeberg and Hannu Tenhunen

03:00-03:10 Short Break

03:10-04:00 Session 7 – Test Compaction and Compression

Marco Ottavi, University of Rome "Tor Vergata"

7.1R Compacting Output Responses Containing Unknowns Using an Embedded Processor

Kamran Saleem, Sreenivaas Muthyala and Nur Touba

7.2R Impact of Test Compression on Power Supply Noise Control

Tengteng Zhang and D. M. H. Walker

7.3S Improving X-Tolerant Combinational Output Compaction via Input Rotation

Asad Bawa and Nur Touba

04:00-04:30 Coffee Break

04:30-05:30 Session 8 – Resilient Design and Technology

Lorena Anghel, TIMA Laboratory

8.1R Low-Power LDPC Decoder Design Exploiting Memory Error Statistics

Junlin Chen and Lei Wang

8.2R SEU sensitivity and modeling using picosecond pulsed laser stimulation of a D Flip-Flop in 40 nm CMOS technology

Clement Champeix, Nicolas Borrel, Jean-Max Dutertre, Bruno Robisson, Mathieu Lisart and Alexandre Sarafianos

8.3S Approximate Compressors for Error-Resilient Multiplier Design

Zhixi Yang, Jie Han and Fabrizio Lombardi

8.4S Characterization of low power radiation-hard Reed-Solomon code protected serializers in 65-nm for HEP experiments electronics

Daniele Felici, Sandro Bonacini and Marco Ottavi

05:30-06:30 DFT TPC meeting

Wednesday October 14, 2015

08:00-09:00 Keynote Talk: "Building a Resilient Internet of Things"
                       Rob Aitken, ARM

Maria K. Michael, University of Cyprus

09:00-10:10 Session 9 – Resiliency in Many-core Systems

Cristiana Bolchini, Politecnico di Milano

9.1R Reducing the Performance Overhead of Resilient CMPs with Substitutable Resources

Alirad Malek, Stavros Tzilis, Danish Anish Khan, Ioannis Sourdis, Georgios Smaragdos and Christos Strydis

9.2R Dependable Real-Time Task Execution Scheme for a Many-core Platform

Tomohiro Yoneda, Masashi Imai, Hiroshi Saito and Kenji Kise

9.3R Towards Reliability and Performance-Aware Wireless Network-on-Chip Design

Michael Opoku Agyeman, Kenneth Tong and Terrence Mak

9.4S A Fast and Scalable Fault Injection Framework to Evaluate Multi/Many-core Soft Error Reliability

Felipe Rosa, Fernanda Kastensmidt, Ricardo Reis and Luciano Ost

10:10-10:40 Coffee Break

10:40-11:50 Session 10 - Error Prediction, Detection and Diagnosis

Felipe França, Federal University of Rio de Janeiro

10.1R A Cross-layer Approach to Online Adaptive Reliability Prediction of Transient Faults

Bahar Farahani and Saeed Safari

10.2R A non-conservative software-based approach for detecting illegal CFE's caused by transient faults

Diego Rodrigues, Ghazaleh Nazarian, Álvaro Moreira, Luigi Carro and Georgi Gaydadjiev

10.3R A Configurable Board-level Adaptive Incremental Diagnosis Technique based on Decision Trees

Cristiana Bolchini and Luca Cassano

10.4S IntelliCAN: Attack-Resilient Controller Area Network (CAN) for Secure Automobiles

Mohammad Raashid Ansari, Shucheng Yu and Qiaoyan Yu

11:50-12:00 Conference Closing

12:00 Boxed Lunch

x.xR – Indicates Regular paper (18’ presentation + 2’ Q&A)
x.xS – Indicates Short paper (8’ presentation + 2’ Q&A)

It is possible to download the flyer of the program here.