IEEE Int. Symposium on Defect and Fault Tolerance
 in VLSI and Nanotechnology Systems
 IEEE Int. Symposium on Defect and Fault Tolerance
 in VLSI and Nanotechnology Systems

Welcome to DFT 2017 in Cambridge, UK


DFT is an annual Symposium providing an open forum for presentations in the field of defect and fault tolerance in VLSI and nanotechnology systems inclusive of emerging technologies. One of the unique features of this symposium is to combine new academic research with state-of-the-art industrial data, necessary ingredients for significant advances in this field. All aspects of design, manufacturing, test, reliability, and availability that are affected by defects during manufacturing and by faults during system operation are of interest.

A detailed list of the topics of interest is available here.

For its 30th edition DFT is coming to Europe and to Cambridge, UK.

Special issue in IET Computers & Digital Techniques

The CfP for the special issue in the IET Computers & Digital Techniques journal is now available (the flier is available here). Please consider this opportunity to submit an extended version of your DFT-2017 paper. You are certainly welcome to submit another relevant work, not previously submitted to DFT-2017.

Please find all information here.

Award Winners

  • Best Paper Award: "Eliminating a Hidden Error Source in Stochastic Circuits" by Paishun Ting and John Hayes
  • Best Student Paper Award: "RASSS: A Perfidy-Aware Protocol for Designing Trustworthy Distributed Systems" by Lake Bu, Hien D. Nguyen and Michel A. Kinsy
  • 1st Runner-up Best Student Paper Award: "On-Line Software-based Self-Test for ECC of Embedded RAM Memories" by Marco Restifo, Paolo Bernardi, Alessandro Sansonetti and Sergio De Luca

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