Special Issue 2025

We are glad to announce the Special Issue on Defect and Fault Tolerance in VLSI and Nanotechnology Systems associated with the 38th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS 2025) and hosted by Microprocessors and Microsystems (MICPRO) journal.

DFTS 2025 Special Issue in Microprocessors and Microsystems (MICPRO) journal

Defect and fault tolerance in VLSI and nanotechnology systems including emerging technologies, RISC-V architectures and AI solutions, are pervasive topics. This special issue features both new academic research and state-of-the-art industrial data, necessary ingredients for advances in this field. All aspects of digital (embedded) systems design, manufacturing, test, reliability, availability, and security that affected by defects during manufacturing and by faults during operation are of interest. Topics include (but are not limited to) the following:

  1. Yield Analysis and Modeling:
    Defect/fault analysis and models; statistical yield modeling; diagnosis; critical area and other metrics.
  2. Testing Techniques:
    Built-in self-test; delay fault modeling and diagnosis; testing for analog and mixed circuits; online testing.
  3. Design For Testability in IC Design:
    FPGA, SoC, NoC, ASIC, low-power design and micro-processors, including RISC-V architectures
  4. Error Detection, Correction, and Recovery:
    Self-testing and self-checking solutions; error-control coding; fault masking and avoidance; recovery schemes; space/time redundancy; HW/SW techniques; architectural and system-level techniques.
  5. Dependability Analysis and Validation:
    Fault injection techniques and frameworks; dependability and characterization; cross-layer reliability analysis; dependability analysis for AI and machine learning.
  6. Repair, Restructuring and Reconfiguration:
    Repairable logic; reconfigurable circuit design; DFT for on-line operation; self-healing; reliable FPGAs.
  7. Defect and Fault Tolerance:
    Reliable circuit synthesis; fault tolerant design; design space exploration for dependable systems.
  8. Radiation effects:
    SEEs on nanotechnologies; modeling of radiation environments; radiation experiments; radiation hardening.
  9. Aging and Lifetime Reliability:
    Aging characterization and modeling; design and run-time reliability. Variability management and recovery.
  10. Dependable Applications and Case Studies:
    Methodologies and case studies: 2.5D/3D ICs, IoT, automotive/railway/avionics/space, autonomous systems, industrial control, fail-safe systems, dependable AI.
  11. Emerging Technologies:
    Error management techniques for memristors, spintronics, microfluidics, approximate computing, etc.
  12. Design for Security:
    Fault attacks; fault tolerance-based countermeasures; scan-based attacks and countermeasures; hardware trojans; system obfuscation; secure AI. Interactions between VLSI test, trust, and reliability.

Extended journal versions of papers from the 38th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems 2025 are welcome. Extended papers must contain at least 30% of new material different from the original work published in the conference proceedings preferably with a reformulated text of the unmodified parts.

Important dates

Submission Deadline 19 December 2025
9 January 2026
First Round Decisions 20 March 2026
Revised Papers Submission 15 May 2026
Decisions for the Revisions 3 July 2026
Camera Ready Deadline 17 July 2026

Manuscript submission information

To submit your manuscript:

The article should not exceed 12 pages, including the references. Please read the Guide for Authors submission instructions.

Please address all other correspondence regarding this special issue to the Guest Editors.
Guest Editors
Dr. Petr FiĊĦer
Czech Technical University in Prague, Faculty of Information Technology.
fiserp@fit.cvut.cz 		Dr. Adrian Evans
Research Engineer CEA/LIST, Grenoble France
adrian.evans@cea.fr