The DFT 2019 Symposium will be hosted by European Space Research and Technology Centre (ESTEC) on the 2nd and 3rd of October and by Delft University of Technology (TU Delft) on the 4th of October.

ESTEC is located in Keplerlaan 1, 2201 AZ Noordwijk

TU Delft is located in Mekelweg 5, 2628 CD Delft


Latest Update

  • Tentative program available here
  • Camera-ready submission postponed: August 20
  • Paper notification postponed: July 19
  • Deadline extension: full paper submission on May 24
  • Deadline extension: abstract submission on May 10
  • Call for papers special sessions available pdf
  • Call for papers available pdf
  • The new site is up

Call for Contributions

Call for papers

PDF Version

Abstract submissions May 10, 2019 May 3, 2019
Full paper submissions May 24, 2019 May 17, 2019
Notification July 19, 2019 July 12, 2019
Camera ready and author's registration August 20, 2019 August 9, 2019


DFT is an annual Symposium providing an open forum for presentations in the field of defect and fault tolerance in VLSI and nanotechnology systems inclusive of emerging technologies. One of the unique features of this symposium is to combine new academic research with state-of-the-art industrial data, necessary ingredients for significant advances in this field. All aspects of design, manufacturing, test, reliability, and availability that are affected by defects during manufacturing and by faults during system operation ar e of interest. Topics include (but are not limited to) the following:

      • Yield Analysis and Modeling
        Defect/fault analysis and models; statistical yield modeling; diagnosis; critical area and other metrics.
      • Testing Techniques
        Built-in self-test; delay fault modeling and diagnosis; testing for analog and mixed circuits; online testing; signal and clock integrity.
      • Design For Testability in IC Design
        FPGA, SoC, NoC, ASIC, low power design and microprocessors.
      • Error Detection, Correction, and Recovery
        Self-testing and self-checking solutions; error-control coding; fault masking and avoidance; recovery schemes, space/time redundancy; hw/sw techniques; architectural and system-level techniques.
      • Dependability Analysis and Validation
        Fault injection techniques and frameworks; dependability and characterization.
      • Repair, Restructuring and Reconfiguration
        Repairable logic; reconfigurable circuit design; DFT for on-line operation; self-healing; reliable FPGA-based systems.
      • Defect and Fault Tolerance
        Reliable circuit/system synthesis; fault tolerant processes and design; design space exploration for dependable systems, transient/soft faults.
      • Radiation effects
        SEEs on nanotechnologies; modeling of radiation environments; radiation experiments; radiation hardening techniques.
      • Aging and Lifetime Reliability
        Aging characterization and modeling; design and run-time reliability, thermal, and variability management and recovery.
      • Dependable Applications and Case Studies
        Methodologies and case studies for IoTs, automotive, railway, avionics and space, autonomous systems, industrial control, etc.
      • Emerging Technologies
        Techniques for 2.5D/3D ICs, quantum computing architecttures, memristors, spintronics, microfluidics, etc.
      • Design for Security
        Fault attacks, fault tolerance-based countermeasures, scan-based attacks and countermeasures, hardware trojans, security vs. reliability trade-offs, interaction between VLSI test, trust, and reliability.

Call for Special Sessions

PDF Version

DFT’19 seeks proposals for Special Sessions. The special sessions should aim at providing a complementary experience with respect to the regular sessions by focusing on hot and emerging topics of interest to the DFT community, as well as on multi-disciplinary topics, that are expected to have a significant impact on DFT activities in the future (e.g. reliability aspects in Approximate Computing, Quantum Computing, use of COTS Electronics for Space applications). A special session could consist of a set of individual presentations or a panel, possibly with experts from the industry.

Upon acceptance, special session presenters can prepare either a single paper for the entire session or one paper per presenter to be included in the formal proceedings. For this reason, papers (presenting original and unpublished contributions and that may be 4 pages or 6 pages long) for special session will go through review process. For the single-session papers, it will be possible to purchase 2 extra pages at an additional cost. Accepted papers will appear in the formal proceedings of DFT 2019 symposium. Proceedings will be published by the IEEE Computer Society and will appear in the Digital Library

Submission Process: Submitted proposals should include:

      • a title of the special session
      • a maximum 250-word abstract outlining the session's scope, topics and relevance for DFT symposium
      • name, contact information and short biography of the organizer(s)
      • format of the session: (1) panel or set of individual presentations, and (2) single paper per session or one paper per presenter
      • list of three/four contributed presentations (including titles, presenter names, contact information of the corresponding presenter, and an abstract of each contribution). For panel proposals, list three to five panelists and their area of expertise.

Proposal submissions should be presented in a single PDF to be sent via e-mail to the Special Session Chair:

      • Luigi Dilillo - dilillo at lirmm dot fr

By means of their submission, all presenters agree to register for and participate to DFT’19, in case their special session proposal is accepted.

Important Dates

Special session proposal due May 10, 2019 May 3, 2019
Special session acceptance May 17, 2019
Special session paper submission June 9, 2019
Paper acceptance notification July 9, 2019
Camera ready and author's registration August 20, 2019 July 23, 2019


DFT 2019

32nd IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems
October 2 – October 4, 2019, ESA-ESTEC & TU Delft, Netherlands

This document provides instructions for submitting papers to the 32nd edition of the IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2019. In an effort to respect the efforts of reviewers and in the interest of fairness to all prospective authors, we request that all submissions to DFT’19 follow the formatting and submission rules detailed below. Submissions that violate these instructions may not be reviewed, at the discretion of the program chair, in order to maintain a review process that is fair to all potential authors. An example submission (formatted using the DFT’19 submission format) that contains the submission and formatting guidelines can be downloaded from here: Sample PDF. The content of the document mirrors the submission instructions on this page.

Submission Site:

Abstract/paper registration deadline:
May 10, 2019 May 3, 2019

Full paper submission deadline:
May 24, 2019 May 17, 2019

Paper Evaluation

All submissions that meet the criteria and fit the scope of the conference will be reviewed by at least three members of the Technical Program Committee. Submissions will be evaluated on the basis of originality, soundness, importance of contribution, quality of presentation, and appropriate comparison to related work. The Program Co-Chairs will make the final decisions about which submissions are accepted for presentation at the conference.

Paper Preparation Instructions

Paper Formatting

Papers must be submitted in printable PDF format and should contain a maximum of 6 pages (or 4 pages for short papers) of single-spaced two-column text, Times or equivalent font of minimum 10pt, including any appendixes and references. Use either the MS Word template or the LaTeX class available here:  IEEE templates. If you are usign LaTeX, please specify


Paper Submission Instructions

Submission website

Submissions are managed by means of EasyChair. Please register or use your existing login at EasyChair to access the DFT 2019 area for submission at:


Declaring Authors

Declare all the authors of the paper upfront. Addition/removal of authors once the paper is accepted will have to be approved by the program chair, since it potentially undermines the goal of eliminating conflicts for reviewer assignment.

Concurrent Submissions and Workshops

By submitting a manuscript to DFT’19, the authors guarantee that the manuscript has not been previously published or accepted for publication in a substantially similar form in any conference, journal, or workshop. The only exceptions are (1) workshops without archived proceedings such as in the ACM/IEEE digital library (or where the authors chose not to have their paper appear in the archived proceedings), or (2) venues, such as IEEE CAL, where there is an explicit policy that such publication does not preclude longer conference submissions. These are not considered prior publications.  Technical reports and papers posted on public social media sites, Web pages, or online repositories, such as arxiv.org, are not considered prior publications either. The authors also guarantee that no paper that contains significant overlap with the contributions of the submitted paper will be under review for any other conference, journal, or workshop during the DFT’19 review period. Violation of any of these conditions will lead to rejection.  As always, if you are in doubt, it is best to contact the program chair(s).  Finally, we also note that the IEEE Plagiarism Policy (http://www.ieee.org/publications/policies/plagiarism_policy) covers a range of ethical issues concerning the misrepresentation of other works or one's own work.


Organizing Committee

General Chairs Marco Ottavi University of Rome "Tor Vergata", IT marco.ottavi@uniroma2.it
Antonios Tavoularis European Space Agency, NL antonios.tavoularis@esa.int
Program Chairs Vilas Sridharan AMD, USA vilas.sridharan@amd.com
Mihalis Psarakis University of Piraeus, GR mpsarak@unipi.gr
Special Session Luigi Dilillo LIRMM, FR luigi.dilillo@lirmm.fr
Finance Marco Rovatti European Space Agency, NL
Publicity/Web Luca Cassano Politecnico di Milano, IT
Publication Prashant Nair University of British Columbia
Local Arrangements Gianluca Furano European Space Agency, NL
Alessandra Menicucci TU Delft, NL
Industrial Liasons TBA

Technical Program Committee

L. Anghel TIMA, FR
G. Beltrame École Polytechnique de Montréal, CA
E. Bezerra UFSC, BR
C. Bolchini Politecnico di Milano, IT
L. Cassano Politecnico di Milano, IT
G. Chapman Simon Fraser University, CA
L. Dilillo LIRMM, FR
S. Eggersgluess Mentor Graphics, US
O. Ergin TOBB University, TR
G. Furano European Space Agency, NL
D. Gizopoulos University of Athens, GR
J. Han University of Alberta, CA
D. Hely Grenoble INP, FR
C. Huang National Tsing Hua University, TW
H. Ichihara Hiroshima City University, JP
V. Izosimov Semcon AB, SE
X. Jian Virginia Tech, US
P. Joshi Intel, US
N. Karimi University of Maryland, US
S. Khursheed University of Liverpool, UK
Y-B Kim Northeastern University, US
B. Kruseman NXPSemiconductors, NL
F. Lombardi Northeastern University, US
E. Marinissen IMEC, NL
D. Melo University of Vale do Itajai, BR
A. Menicucci University of Delft, NL
M. Michael University of Cyprus, CY
A. Miele Politecnico di Milano, IT
M. Kermani University of South Florida, US
P. Nair University of British Columbia, US
K. Namba Chiba University, JP
N. Nicolici McMaster University, CA
C. Nicopoulos University of Cyprus, CY
M. Ottavi Univ. of Rome “Tor Vergata”, IT
I. Polian University of Passau, DE
M. Psarakis University of Piraeus, GR
A. Rahmani UC Irvine, US and TU Wien, AT
P. Reviriego Universidad Carlos III de Madrid, ES
D. Rossi, University of Hertfordshire, UK
M. Rovatti European Space Agency, NL
C. Sandionigi CEA, FR
R. Shafik School of EEE, Newcastle University, UK
M. Shafique Vienna University of Technology, AT
T. Siddiqua AMD, US
I. Sourdis Chalmers Univ. of Technology, SE
V. Sridharan AMD, US
M. Taouil Delft University of Technology, NL
A. Tavoularis European Space Agency, NL
P. Teixeira IST/INESC-ID, PT
N. Touba University of Texas at Austin, US
S. Tragoudas Southern Illinois University, US
B. Venu ARM Ltd, UK
Q. Xu The Chinese University of Hong Kong, HK
G. Yalcin Abdullah Gul University, TR
T. Yoneda Tokyo Institute of Technology, JP