DFT (International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems) is an annual Symposium providing an open forum for presentations in the field of defect and fault tolerance in VLSI systems inclusive of emerging technologies. One of the unique features of this symposium is to combine new academic research with state-of-the-art industrial data, necessary ingredients for significant advances in this field.
In 2015 DFT will be hosted at the University of Massachusetts Amherst.
The organizing committee is finalizing the dates of the event and as soon as they are available they will be posted here.
Authors of the papers presented at DFT 2014 are welcome to submit an extended version (at least 40% of new content and complete paper re-writing) of their work to a Joint Special Section on Defect and Fault Tolerance in VLSI and Nanotechnology Systems that will appear on the IEEE Trans. on Computers and on the IEEE Trans. on Nanotechnology. More details here.
Thank you note
On behalf of DFT Conference we would like to thank everyone who contributed to our 27th Annual International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems. We have received very good feedback from the attendees for the excellent technical program. The conference social event allowed ample time to network with each other. Who could ever forget an actual cruise ship in the background of presentation screen!!
The excellent keynote by Prof. Josep Torrellas ended with a very good note for the attendees with a call for renewed focus on various sources of errors and a need to detect and address them online. We hope to see you at the next year's event and thank you for your continued support.
Said Hamdioui (Delft University of Technology, Netherlands)
Marco Ottavi (University of Rome "Tor Vergata", Italy)
Sandip Kundu (University of Massachusetts, Amherst, USA)
Salvatore Pontarelli (CNIT, Italy)