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Call for Contributions

Call for papers

PDF Version

Abstract submissions                                      May 4, 2018April 27, 2018
Full paper submissions                                    May 18, 2018May 11, 2018
Notification                                                            July 6, 2018
Camera ready and author's registration      July 27, 2018

 

DFT is an annual Symposium providing an open forum for presentations in the field of defect and fault tolerance in VLSI and nanotechnology systems inclusive of emerging technologies. One of the unique features of this symposium is to combine new academic research with state-of-the-art industrial data, necessary ingredients for significant advances in this field. The research may target diverse aspects of design, manufacturing, test, reliability, and availability that are affected by defects during manufacturing and by faults during system operation.

Areas of interest include, but are not limited to:

      • Yield Analysis and Modeling
        Defect/fault analysis and models; statistical yield modeling; diagnosis; critical area and other metrics.
      • Testing Techniques
        Built-in self-test; delay fault modeling and diagnosis; testing for analog and mixed circuits; online testing; signal and clock integrity.
      • Design For Testability in IC Design
        FPGA, SoC, NoC, ASIC, low power design and microprocessors.
      • Error Detection, Correction, and Recovery
        Self-testing and self-checking design; error-control coding; fault masking and avoidance; recovery schemes, space/time redundancy; hw/sw techniques; architectural-specific techniques; system-level design-time or runtime strategies.
      • Dependability Analysis and Validation
        Fault injection techniques and frameworks; system's dependability and vulnerability characterization.
      • Repair, Restructuring and Reconfiguration
        Repairable logic; reconfigurable circuit design; DFT for on-line operation; self-healing; reliable FPGA-based systems.
      • Design for Defect and Fault Tolerance
        Reliable circuit/system synthesis; radiation hardened/tolerant processes and design; design space exploration for dependable systems; transient/soft faults and errors.
      • Aging and Lifetime Reliability
        Aging characterization and modeling; design and run-time reliability, thermal, and variability management and recovery.
      • Dependable Applications and Case Studies
        Methodologies and case study applications to Internet of Things, automotive, railway, avionics and space, autonomous systems, industrial control, etc.
      • Emerging Technologies
        Techniques for 3D stacked ICs, quantum computing architectures, microfluid biochips, etc.
      • Design for Security
        Fault attacks; fault tolerance-based countermeasures; hw security assurance, hw trojans, resistance to persistent DoS, security vs. reliability trade-offs, interaction between VLSI test, trust, and reliability.

Call for Special Sessions

PDF Version (available soon)

DFT’18 seeks proposals for Special Sessions. The special sessions should aim at providing a complementary experience with respect to the regular sessions by focusing on hot and emerging topics of interest to the DFT community, as well as on multi-disciplinary topics, that are expected to have a significant impact on DFT activities in the future (e.g. reliability aspects in Internet-of-Things, autonomous systems or medical appliances, ...). A special session could consist of a set of individual presentations or a panel, possibly with experts from the industry. Upon acceptance, special session presenters can prepare either a single paper for the entire session or one paper per presenter to be included in the formal proceedings. For this reason, papers (presenting original and unpublished contributions and that may be 4 pages or 6 pages long) for special session will go through review process. For the single-session papers, it will be possible to purchase 2 extra pages at an additional cost.

Submission Process: Submitted proposals should include:

      • a title of the special session
      • a maximum 250-word abstract outlining the session's scope, topics and relevance for DFT symposium
      • name, contact information and short biography of the organizer(s)
      • format of the session: (1) panel or set of individual presentations, and (2) single paper per session or one paper per presenter
      • list of three/four contributed presentations (including titles, presenter names, contact information of the corresponding presenter, and an abstract of each contribution). For panel proposals, list three to five panelists and their area of expertise.

Proposal submissions should be presented in a single PDF to be sent via e-mail to both Program Chairs:

      • Marco Ottavi - ottavi at ing dot uniroma2 dot it
      • Vilas Sridharan - vilas dot sridharan at amd dot com

By means of their submission, all presenters agree to register for and participate to DFT’18, in case their special session proposal is accepted.

Important Dates
Special session proposal due: May 4, 2018April 27, 2018
Special session acceptance: May 18, 2018May 11, 2018
Special session paper submission: June 1, 2018
Paper acceptance notification: July 6, 2018
Camera ready and author's registration: July 27, 2018

Submissions

DFT 2018

31st IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems
Chicago, IL, U.S.A, October, 2018

This document provides instructions for submitting papers to the 31st edition of the IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2018. In an effort to respect the efforts of reviewers and in the interest of fairness to all prospective authors, we request that all submissions to DFT’18 follow the formatting and submission rules detailed below. Submissions that violate these instructions may not be reviewed, at the discretion of the program chair, in order to maintain a review process that is fair to all potential authors. An example submission (formatted using the DFT’18 submission format) that contains the submission and formatting guidelines can be downloaded from here: Sample PDF. The content of the document mirrors the submission instructions on this page.

Submission Site:

Abstract/paper registration deadline:
May 4, 2018 (11:59:59pm US eastern time)

Full paper submission deadline:
May 18, 2018 (11:59:59pm US eastern time)

Paper Evaluation

All submissions that meet the criteria and fit the scope of the conference will be reviewed by at least three members of the Technical Program Committee. Submissions will be evaluated on the basis of originality, soundness, importance of contribution, quality of presentation, and appropriate comparison to related work. The Program Co-Chairs will make the final decisions about which submissions are accepted for presentation at the conference.

Paper Preparation Instructions

Paper Formatting

Papers must be submitted in printable PDF format and should contain a maximum of 6 pages (or 4 pages for short papers) of single-spaced two-column text, Times or equivalent font of minimum 10pt, including any appendixes and references. Use either the MS Word template or the LaTeX class available here:  IEEE templates. If you are usign LaTeX, please specify

\documentclass[conference]{IEEEtran}
.

Paper Submission Instructions

Declaring Authors

Declare all the authors of the paper upfront. Addition/removal of authors once the paper is accepted will have to be approved by the program chair, since it potentially undermines the goal of eliminating conflicts for reviewer assignment.

Concurrent Submissions and Workshops

By submitting a manuscript to DFT’18, the authors guarantee that the manuscript has not been previously published or accepted for publication in a substantially similar form in any conference, journal, or workshop. The only exceptions are (1) workshops without archived proceedings such as in the ACM/IEEE digital library (or where the authors chose not to have their paper appear in the archived proceedings), or (2) venues, such as IEEE CAL, where there is an explicit policy that such publication does not preclude longer conference submissions. These are not considered prior publications.  Technical reports and papers posted on public social media sites, Web pages, or online repositories, such as arxiv.org, are not considered prior publications either. The authors also guarantee that no paper that contains significant overlap with the contributions of the submitted paper will be under review for any other conference, journal, or workshop during the DFT’18 review period. Violation of any of these conditions will lead to rejection.  As always, if you are in doubt, it is best to contact the program chair(s).  Finally, we also note that the IEEE Plagiarism Policy (http://www.ieee.org/publications/policies/plagiarism_policy) covers a range of ethical issues concerning the misrepresentation of other works or one's own work.

Committees

Organizing Committee

General Chairs Spyros Tragoudas Southern Illinois University Carbondale
  Saqib Khursheed University of Liverpool
Program Chairs Marco Ottavi University of Rome "Tor Vergata"
  Vilas Sridharan AMD
Finance Saqib Khursheed University of Liverpool
Publicity Mihalis Psarakis University of Piraeus
Publication Rishad Shafik New Castle University
Industrial Liasons Prashant Joshi Cadence

Technical Program Committee

L. Anghel TIMA, FR
G. Beltrame École Polytechnique de Montréal, CA
C. Bolchini Politecnico di Milano, IT
L. Cassano Politecnico di Milano, IT
G. Chapman Simon Fraser University, US
J. Dworak Southern Methodist University, US
M. Ebrahimi KTH Royal Inst. Technology, SE
S. Eggersgluess University of Bremen, DE
O. Ergin TOBB University, TR
A. Evans CEA-LETI DACLE, MINATEC, FR
G. Furano ESA, NL
D. Gizopoulos University of Athens, GR
J. Han University of Alberta, CA
S. Hari nVidia, US
P. Harrod ARM, UK
L. Hernandez Liverpool University, UK
C. Huang National Tsing Hua University, TW
H. Ichihara Hiroshima City University, JP
V. Izosimov KTH Royal Inst. Technology, SE
X. Jan Virginia Tech, US
P. Joshi Cadence, US
A. Kanuparthi Intel Corporation, US
N. Karimi University of Maryland, US
R. Karri NYU Polytechnic, US
M. Kermani USF, US
S. Khursheed Liverpool University, UK
Y. Kim, Northeastern University, US
I. Koren Univ. of Massachusetts-Amherst, US
B. Kruseman NXP, NL
S. Kundu Univ. of Massachusetts-Amherst, US
H. Li Chinese Academy of Science, CN
F. Lombardi Northeastern University, US
J. Mathew IIT Patna, IN
S. Menon Intel Corporation, US
C. Metra University of Bologna, IT
M. Michael University of Cyprus, CY
A. Miele Politecnico di Milano, IT
K. Namba Chiba University, JP
N. Nicolici McMaster University, CA
C. Nicopoulos University of Cyprus, CY
M. Ottavi Univ. of Rome “Tor Vergata”, IT
I. Polian University of Passau, DE
I. Pomeranz Purdue University, US
S. Pontarelli Univ. of Rome “Tor Vergata”, IT
M. Psarakis University of Piraeus, GR
A. Rahmani Univ. of California Irvine, US
P. Rech UFRGS, BR
S. Reddy University of Iowa, US
P. Reviriego Universidad Nebrija, ES
D. Rossi, University of Hertfordshire, UK
C. Sandionigi CEA, FR
M. Schölzel Univ. of Potsdam Germany
M. Shafique Technische Universität Wien, AT
R. Shafik New Castle University, UK
T. Siddiqua AMD, US
I. Sourdis Chalmers Univ. of Technology, SE
V. Sridharan AMD, US
M. Taouil TU Delft, NL
J.P. Teixeira IST/INESC-ID, PT
N. Touba University of Texas at Austin, US
S. Tragoudas S. Illinois Univ Carbondale, US
B. Venu ARM, UK
G. Yalcin Abdullah Gul University, TR
T. Yoneda National Institute of Informatics, JP
Q. Yu University of New Hampshire

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