IEEE Int. Symposium on Defect and Fault Tolerance
 in VLSI and Nanotechnology Systems
  
 IEEE Int. Symposium on Defect and Fault Tolerance
 in VLSI and Nanotechnology Systems
  

Welcome to DFT 2017 in Cambridge, UK

 

DFT is an annual Symposium providing an open forum for presentations in the field of defect and fault tolerance in VLSI and nanotechnology systems inclusive of emerging technologies. One of the unique features of this symposium is to combine new academic research with state-of-the-art industrial data, necessary ingredients for significant advances in this field. All aspects of design, manufacturing, test, reliability, and availability that are affected by defects during manufacturing and by faults during system operation are of interest.

A detailed list of the topics of interest is available here.

For its 30th edition DFT is coming to Europe and to Cambridge, UK.

Highlights

Registration and camera ready

Registration website is now open. More information is available here.

For camera ready preparation, click here.

Author registration and camera ready submission deadline: August 4, 2017

Call for demos

This year DFT will give the opportunity to participants to demonstrate their research outcome in a demo session. More information is available here.

Keynote speeches

  • Erik Jan Marinissen, from IMEC
  • Prof. Krishnendu Chakrabarty, from the Duke University
  • Peter Harrod, from ARM
Click here for more information.

Sponsored by