DFT (International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems) is an annual Symposium providing an open forum for presentations in the field of defect and fault tolerance in VLSI systems inclusive of emerging technologies. One of the unique features of this symposium is to combine new academic research with state-of-the-art industrial data, necessary ingredients for significant advances in this field.
In 2015 DFT will be hosted at the University of Massachusetts Amherst.
October 12-14, 2015.
Call for papers
The up-to-date call for paper is available here.
Authors will have the opportunity to submit an extended version of their paper presented at the symposium for a Issue/Special Section scheduled to appear in the last issue of 2016 in IEEE Transaction on Emerging Topics in Computing. More details here.
The following keynote talks are planned for the event!
David Brooks, Oct. 12, TBD
Rob Aitken, Oct. 14, Building a Resilient Internet of Things
Rob Aitken is an ARM Fellow and technology lead for ARM Research. His areas of responsibility include low power design, library architecture for advanced process nodes, and design for manufacturability. His research interests include design for variability, resilient computing, and memory robustness. His group has participated in numerous chip tape-outs, including 8 at or below the 16nm node. He has published over 70 technical papers, on a wide range of topics. Dr. Aitken joined ARM as part of its acquisition of Artisan Components in 2004. Prior to Artisan, he worked at Agilent and HP. He has given tutorials and short courses on several subjects at conferences and universities worldwide. He holds a Ph.D. from McGill University in Canada. Dr. Aitken is an IEEE Fellow, and serves on a number of conference and workshop committees.
Please follow the guidelines available here.