Call for papers
|Abstract submissions||April 24, 2020|
|Full paper submissions||May 8, 2020|
|Notification||July 3, 2020|
|Camera ready and author's registration||July 31, 2020|
DFT is an annual Symposium providing an open forum for presentations in the field of defect and fault tolerance in VLSI and nanotechnology systems inclusive of emerging technologies. One of the unique features of this symposium is to combine new academic research with state-of-the-art industrial data, necessary ingredients for significant advances in this field. All aspects of design, manufacturing, test, reliability, and availability that are affected by defects during manufacturing and by faults during system operation ar e of interest. Topics include (but are not limited to) the following:
- Yield Analysis and Modeling
Defect/fault analysis and models; statistical yield modeling; diagnosis; critical area and other metrics.
- Testing Techniques
Built-in self-test; delay fault modeling and diagnosis; testing for analog and mixed circuits; online testing; signal and clock integrity.
- Design For Testability in IC Design
FPGA, SoC, NoC, ASIC, low power design and microprocessors.
- Error Detection, Correction, and Recovery
Self-testing and self-checking solutions; error-control coding; fault masking and avoidance; recovery schemes, space/time redundancy; hw/sw techniques; architectural and system-level techniques.
- Dependability Analysis and Validation
Fault injection techniques and frameworks; dependability and characterization.
- Repair, Restructuring and Reconfiguration
Repairable logic; reconfigurable circuit design; DFT for on-line operation; self-healing; reliable FPGA-based systems.
- Defect and Fault Tolerance
Reliable circuit/system synthesis; fault tolerant processes and design; design space exploration for dependable systems, transient/soft faults.
- Radiation effects
SEEs on nanotechnologies; modeling of radiation environments; radiation experiments; radiation hardening techniques.
- Aging and Lifetime Reliability
Aging characterization and modeling; design and run-time reliability, thermal, and variability management and recovery.
- Dependable Applications and Case Studies
Methodologies and case studies for IoTs, automotive, railway, avionics and space, autonomous systems, industrial control, etc.
- Emerging Technologies
Techniques for 2.5D/3D ICs, quantum computing architecttures, memristors, spintronics, microfluidics, etc.
- Design for Security
Fault attacks, fault tolerance-based countermeasures, scan-based attacks and countermeasures, hardware trojans, security vs. reliability trade-offs, interaction between VLSI test, trust, and reliability.
- Yield Analysis and Modeling
33rd IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems
October 19 – October 21, 2020, ESA-ESRIN, Frascati, Italy
This document provides instructions for submitting papers to the 33rd edition of the IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2020. In an effort to respect the efforts of reviewers and in the interest of fairness to all prospective authors, we request that all submissions to DFT’20 follow the formatting and submission rules detailed below. Submissions that violate these instructions may not be reviewed, at the discretion of the program chair, in order to maintain a review process that is fair to all potential authors. An example submission (formatted using the DFT’20 submission format) that contains the submission and formatting guidelines can be downloaded from here: Sample PDF. The content of the document mirrors the submission instructions on this page.
Submission Site:Abstract/paper registration deadline: April 24, 2020 Full paper submission deadline: May 8, 2020
All submissions that meet the criteria and fit the scope of the conference will be reviewed by at least three members of the Technical Program Committee. Submissions will be evaluated on the basis of originality, soundness, importance of contribution, quality of presentation, and appropriate comparison to related work. The Program Co-Chairs will make the final decisions about which submissions are accepted for presentation at the conference.
Paper Preparation Instructions
Papers must be submitted in printable PDF format and should contain a maximum of 6 pages of single-spaced two-column text, Times or equivalent font of minimum 10pt, including any appendixes and references. Use either the MS Word template or the LaTeX class available here: IEEE templates. If you are usign LaTeX, please specify
Paper Submission Instructions
Submissions are managed by means of EasyChair. Please register or use your existing login at EasyChair to access the DFT 2020 area for submission at:https://easychair.org/conferences/?conf=dfts2020
Declare all the authors of the paper upfront. Addition/removal of authors once the paper is accepted will have to be approved by the program chair, since it potentially undermines the goal of eliminating conflicts for reviewer assignment.
Concurrent Submissions and Workshops
By submitting a manuscript to DFT’20, the authors guarantee that the manuscript has not been previously published or accepted for publication in a substantially similar form in any conference, journal, or workshop. The only exceptions are (1) workshops without archived proceedings such as in the ACM/IEEE digital library (or where the authors chose not to have their paper appear in the archived proceedings), or (2) venues, such as IEEE CAL, where there is an explicit policy that such publication does not preclude longer conference submissions. These are not considered prior publications. Technical reports and papers posted on public social media sites, Web pages, or online repositories, such as arxiv.org, are not considered prior publications either. The authors also guarantee that no paper that contains significant overlap with the contributions of the submitted paper will be under review for any other conference, journal, or workshop during the DFT’20 review period. Violation of any of these conditions will lead to rejection. As always, if you are in doubt, it is best to contact the program chair(s). Finally, we also note that the IEEE Plagiarism Policy (http://www.ieee.org/
|General Chairs||Marco Ottavi||University of Rome "Tor Vergata", ITemail@example.com|
|Gianluca Furano||European Space Agency, NLfirstname.lastname@example.org|
|Program Chairs||Mihalis Psarakis||University of Piraeus, GRemail@example.com|
|Luigi Dilillo||LIRMM, FRfirstname.lastname@example.org|
|Special Session||Prashant Joshi||Intel, USAemail@example.com|
|Finance||Marco Rovatti||European Space Agency, NL|
|Publicity/Web||Luca Cassano||Politecnico di Milano, IT|
|Publication||Taniya Siddiqua||AMD, USA|
|Industrial Liasons||Vlias Sridharan||AMD, USA|