The safety and well-being of all conference participants is our priority. After evaluating the current COVID-19 situation, the decision has been made to transform the in-person component of DFT 2020 into an all-digital conference experience – DFT 2020 will now be an online event.

Therefore, DFT 2020 will no longer take place in Frascati (Rome), Italy and will instead take place virtually. The conference dates remain the same – October 19 – 21, 2020. For questions, contact program chairs (, . Proceedings will not be canceled, and publications will continue as planned.


The symposium in its 33rd edition will be supported by the European Space Agency (ESA) and will take place at the ESA’s establishment in Italy, ESA-ESRIN. ESA-ESRIN is the European centre of excellence for exploitation of Earth observation missions at October 19-21, 2020. ESRIN is located in Frascati, a small town close to Rome, which is well-connected by train services with the Rome central station and the Fiumicino International Airport.

ESRIN is located in Largo Galileo Galilei 1, 00044 Frascati (RM), Italy


Latest Update

  • Best paper:
    "On board satellite telemetry forecasting with RNN on RISC-V based multi core processor", Danilo Cappellone, Gianluca Furano, Stefano Di Mascio, Alessandra Menicucci and Marco Ottavi
  • Best student paper:
    "Variation-Aware Test for Logic Interconnects using Neural Networks – A Case Study", Alexander Sprenger, Somayeh Sadeghi-Kohan, Jan Dennis Reimer and Sybille Hellebrand
  • Best student paper:
    "Investigating the Impact of Radiation-Induced Soft Errors on the Reliability of Approximate Computing Systems", Lucas Matana Luza, Daniel Söderström, Georgios Tsiligiannis, Helmut Puchner, Carlo Cazzaniga, Ernesto Sanchez, Alberto Bosio and Luigi Dilillo
  • Best student paper:
    "A Pipelined Multi-Level Fault Injector for Deep Neural Networks", Annachiara Ruospo, Angelo Balaara, Alberto Bosio and Ernesto Sanchez
  • Best student paper:
    "A Multiple Target Test Generation Method for Gate-Exhaustive Faults to Reduce the Number of Test Patterns Using Partial MaxSAT", Ryuki Asami, Toshinori Hosokawa, Masayoshi Yoshimura and Masayuki Arai
  • Instructions for speakers are available here
  • The program is available here
  • Program flyer available
  • IEEE Transactions on Emerging Topics in Computing Special Section on Defect and Fault Tolerance in Nanoscale Systems for Emerging Computing Paradigms and Applications announced here
  • Third keynote speaker announced: Mr Wilfried Steiner, talk title: "Design Rationales for Fail-Operational Safety Platforms"
  • Second keynote speaker announced: Mr Jan Andersson, talk title: "Fault-Tolerance in Current and Future LEON and NOEL-V System-on-Chip Architectures"
  • Deadline extension: full paper submission on June 5
  • First keynote speaker announced: Prof. Luca Benini, talk title: "Living with imprecise computation: an energy efficiency perspective"
  • Call for papers special sessions available pdf
  • Call for papers available pdf
  • The new site is up

Call for Contributions

Call for papers

PDF Version

Full paper submissions June 5, 2020 May 8, 2020
Notification July 10, 2020
Camera ready and author's registration July 31, 2020


DFT is an annual Symposium providing an open forum for presentations in the field of defect and fault tolerance in VLSI and nanotechnology systems inclusive of emerging technologies. One of the unique features of this symposium is to combine new academic research with state-of-the-art industrial data, necessary ingredients for significant advances in this field. All aspects of design, manufacturing, test, reliability, and availability that are affected by defects during manufacturing and by faults during system operation ar e of interest. Topics include (but are not limited to) the following:

      • Yield Analysis and Modeling
        Defect/fault analysis and models; statistical yield modeling; diagnosis; critical area and other metrics.
      • Testing Techniques
        Built-in self-test; delay fault modeling and diagnosis; testing for analog and mixed circuits; online testing; signal and clock integrity.
      • Design For Testability in IC Design
        FPGA, SoC, NoC, ASIC, low power design and microprocessors.
      • Error Detection, Correction, and Recovery
        Self-testing and self-checking solutions; error-control coding; fault masking and avoidance; recovery schemes, space/time redundancy; hw/sw techniques; architectural and system-level techniques.
      • Dependability Analysis and Validation
        Fault injection techniques and frameworks; dependability and characterization.
      • Repair, Restructuring and Reconfiguration
        Repairable logic; reconfigurable circuit design; DFT for on-line operation; self-healing; reliable FPGA-based systems.
      • Defect and Fault Tolerance
        Reliable circuit/system synthesis; fault tolerant processes and design; design space exploration for dependable systems, transient/soft faults.
      • Radiation effects
        SEEs on nanotechnologies; modeling of radiation environments; radiation experiments; radiation hardening techniques.
      • Aging and Lifetime Reliability
        Aging characterization and modeling; design and run-time reliability, thermal, and variability management and recovery.
      • Dependable Applications and Case Studies
        Methodologies and case studies for IoTs, automotive, railway, avionics and space, autonomous systems, industrial control, etc.
      • Emerging Technologies
        Techniques for 2.5D/3D ICs, quantum computing architecttures, memristors, spintronics, microfluidics, etc.
      • Design for Security
        Fault attacks, fault tolerance-based countermeasures, scan-based attacks and countermeasures, hardware trojans, security vs. reliability trade-offs, interaction between VLSI test, trust, and reliability.

Call for Special Sessions

PDF Version

DFT’20 seeks proposals for Special Sessions. The special sessions should aim at providing a complementary experience with respect to the regular sessions by focusing on hot and emerging topics of interest to the DFT community, as well as on multi-disciplinary topics, that are expected to have a significant impact on DFT activities in the future (e.g. reliability aspects in Approximate Computing, Quantum Computing, use of COTS Electronics for Space applications). A special session could consist of a set of individual presentations or a panel, possibly with experts from the industry.

Upon acceptance, special session presenters can prepare either a single paper for the entire session or one paper per presenter to be included in the formal proceedings. For this reason, papers (presenting original and unpublished contributions and that may be 4 pages or 6 pages long) for special session will go through review process. For the single-session papers, it will be possible to purchase 2 extra pages at an additional cost. Accepted papers will appear in the formal proceedings of DFT 2020 symposium. Proceedings will be published by the IEEE Computer Society and will appear in the Digital Library

Submission Process: Submitted proposals should include:

      • a title of the special session
      • a maximum 250-word abstract outlining the session's scope, topics and relevance for DFT symposium
      • name, contact information and short biography of the organizer(s)
      • format of the session: (1) panel or set of individual presentations, and (2) single paper per session or one paper per presenter
      • list of three/four contributed presentations (including titles, presenter names, contact information of the corresponding presenter, and an abstract of each contribution). For panel proposals, list three to five panelists and their area of expertise.

Proposal submissions should be presented in a single PDF to be sent via e-mail to the Special Session Chair:

      • Prashant Joshi -
      • email Object: DFT’20 Special Session Proposal

By means of their submission, all presenters agree to register for and participate to DFT’20, in case their special session proposal is accepted.

Special session proposal due May 8, 2020 April 24, 2020
Special session acceptance May 15, 2020 May 8, 2020
Special session paper submission June 5, 2020
Paper acceptance notification July 10, 2020
Camera ready and author’s registration July 31, 2020


DFT 2020

33rd IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems
October 19 – October 21, 2020, ESA-ESRIN, Frascati, Italy

This document provides instructions for submitting papers to the 33rd edition of the IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2020. In an effort to respect the efforts of reviewers and in the interest of fairness to all prospective authors, we request that all submissions to DFT’20 follow the formatting and submission rules detailed below. Submissions that violate these instructions may not be reviewed, at the discretion of the program chair, in order to maintain a review process that is fair to all potential authors. An example submission (formatted using the DFT’20 submission format) that contains the submission and formatting guidelines can be downloaded from here: Sample PDF. The content of the document mirrors the submission instructions on this page.

Submission Site:

Full paper submission deadline: June 5, 2020 May 8, 2020

Paper Evaluation

All submissions that meet the criteria and fit the scope of the conference will be reviewed by at least three members of the Technical Program Committee. Submissions will be evaluated on the basis of originality, soundness, importance of contribution, quality of presentation, and appropriate comparison to related work. The Program Co-Chairs will make the final decisions about which submissions are accepted for presentation at the conference.

Paper Preparation Instructions

Paper Formatting

Papers must be submitted in printable PDF format and should contain a maximum of 6 pages of single-spaced two-column text, Times or equivalent font of minimum 10pt, including any appendixes and references. Use either the MS Word template or the LaTeX class available here:  IEEE templates. If you are usign LaTeX, please specify


Paper Submission Instructions

Submission website

Submissions are managed by means of EasyChair. Please register or use your existing login at EasyChair to access the DFT 2020 area for submission at:

Declaring Authors

Declare all the authors of the paper upfront. Addition/removal of authors once the paper is accepted will have to be approved by the program chair, since it potentially undermines the goal of eliminating conflicts for reviewer assignment.

Concurrent Submissions and Workshops

By submitting a manuscript to DFT’20, the authors guarantee that the manuscript has not been previously published or accepted for publication in a substantially similar form in any conference, journal, or workshop. The only exceptions are (1) workshops without archived proceedings such as in the ACM/IEEE digital library (or where the authors chose not to have their paper appear in the archived proceedings), or (2) venues, such as IEEE CAL, where there is an explicit policy that such publication does not preclude longer conference submissions. These are not considered prior publications.  Technical reports and papers posted on public social media sites, Web pages, or online repositories, such as, are not considered prior publications either. The authors also guarantee that no paper that contains significant overlap with the contributions of the submitted paper will be under review for any other conference, journal, or workshop during the DFT’20 review period. Violation of any of these conditions will lead to rejection.  As always, if you are in doubt, it is best to contact the program chair(s).  Finally, we also note that the IEEE Plagiarism Policy ( covers a range of ethical issues concerning the misrepresentation of other works or one's own work.


Organizing Committee

General Chairs Marco Ottavi University of Rome "Tor Vergata", IT
Gianluca Furano European Space Agency, NL
Program Chairs Mihalis Psarakis University of Piraeus, GR
Luigi Dilillo LIRMM, FR
Special Session Prashant Joshi Intel, USA
Finance Marco Rovatti European Space Agency, NL
Publicity/Web Luca Cassano Politecnico di Milano, IT
Publication Taniya Siddiqua Microsoft, USA
Industrial Liasons Vlias Sridharan AMD, USA
Audio/Visual Lucas Matana Luza LIRMM, FR

Technical Program Committee

J. Abella Universitat Politecnica de Catalunya, ES
L. Anghel TIMA, FR
E. Bezerra UFSC, BR
C. Bolchini Politecnico di Milano, IT
L. Cassano Politecnico di Milano, IT
G. Chapman Simon Fraser University, CA
G. Di Natale CNRS-TIMA, FR
L. Dilillo LIRMM, FR
S. Eggersgluess Mentor Graphics, US
O. Ergin TOBB University, TR
A. Evans IROC Technologies, FR
D. Forte University of Florida, US
G. Furano European Space Agency, NL
G. Gambardella Xilinx, IR
Z. Gao Tianjin University, CH
D. Gizopoulos University of Athens, GR
J. Han University of Alberta, CA
D. Hely Grenoble INP, FR
C. Huang National Tsing Hua University, TW
H. Ichihara Hiroshima City University, JP
X. Jian Virginia Tech, US
P. Joshi Intel, US
N. Karimi University of Maryland, US
S. Khursheed University of Liverpool, UK
B. Kruseman NXP Semiconductors, NL
F. Lombardi Northeastern University, US
J. Mathew IITP, IN
D. Melo University of Vale do Itajai, BR
S. Menon Intel, US
C. Metra University of Bologna, IT
A. Menicucci University of Delft, NL
M. Michael University of Cyprus, CY
A. Miele Politecnico di Milano, IT
M. Kermani University of South Florida, US
P. Nair University of British Columbia, US
K. Namba Chiba University, JP
N. Nicolici McMaster University, CA
C. Nicopoulos University of Cyprus, CY
M. Olivieri Sapienza Univ. of Rome, IT
M. Ottavi Univ. of Rome “Tor Vergata”, IT
I. Polian University of Stuttgart, DE
M. Psarakis University of Piraeus, GR
A. Rahmani UC Irvine, US and TU Wien, AT
P. Reviriego Universidad Carlos III de Madrid, ES
D. Rossi, University of Hertfordshire, UK
M. Rovatti European Space Agency, NL
R. Shafik School of EEE, Newcastle University, UK
M. Shafique Vienna University of Technology, AT
T. Siddiqua Microsoft, US
I. Sourdis Chalmers Univ. of Technology, SE
V. Sridharan AMD, US
M. Taouil Delft University of Technology, NL
A. Tavoularis European Space Agency, NL
P. Teixeira IST/INESC-ID, PT
N. Touba University of Texas at Austin, US
S. Tragoudas Southern Illinois University, US
B. Venu ARM Ltd, UK
Q. Xu The Chinese University of Hong Kong, HK
G. Yalcin Abdullah Gul University, TR
T. Yoneda Tokyo Institute of Technology, JP