DFT

IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems

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Overview of the conference

DFT is an annual Symposium providing an open forum for presentations in the field of defect and fault tolerance in VLSI and nanotechnology systems inclusive of emerging technologies. One of the unique features of this symposium is to combine new academic research with state-of-the-art industrial data, necessary ingredients for significant advances in this field. All aspects of design, manufacturing, test, reliability, and availability that are affected by defects during manufacturing and by faults during system operation are of interest.

Important dates

Regular Papers

Title and abstract submission
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Paper submission
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Notification
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Camera ready
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Special Sessions

Special session proposal
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Special session paper submission
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Paper acceptance notification
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Camera ready and author’s registration
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Call for papers

PDF Version

DFT is an annual Symposium providing an open forum for presentations in the field of defect and fault tolerance in VLSI and nanotechnology systems inclusive of emerging technologies. One of the unique features of this symposium is to combine new academic research with state-of-the-art industrial data, necessary ingredients for significant advances in this field. All aspects of design, manufacturing, test, reliability, and availability that are affected by defects during manufacturing and by faults during system operation ar e of interest. Topics include (but are not limited to) the following:

  1. Yield Analysis and Modeling
    Defect/fault analysis and models; statistical yield modeling; diagnosis; critical area and other metrics.
  2. Testing Techniques
    Built-in self-test; delay fault modeling and diagnosis; testing for analog and mixed circuits; online testing; signal and clock integrity.
  3. Design For Testability in IC Design
    FPGA, SoC, NoC, ASIC, low power design and microprocessors.
  4. Error Detection, Correction, and Recovery
    Self-testing and self-checking solutions; error-control coding; fault masking and avoidance; recovery schemes, space/time redundancy; hw/sw techniques; architectural and system-level techniques.
  5. Dependability Analysis and Validation
    Fault injection techniques and frameworks; dependability and characterization.
  6. Repair, Restructuring and Reconfiguration
    Repairable logic; reconfigurable circuit design; DFT for on-line operation; self-healing; reliable FPGA-based systems.
  7. Radiation effects
    SEEs on nanotechnologies; modeling of radiation environments; radiation experiments; radiation hardening techniques.
  8. Defect and Fault Tolerance
    Reliable circuit/system synthesis; fault tolerant processes and design; design space exploration for dependable systems, transient/soft faults.
  9. Aging and Lifetime Reliability
    Aging characterization and modeling; design and run-time reliability, thermal, and variability management and recovery.
  10. Dependable Applications and Case Studies
    Methodologies and case studies for IoTs, automotive, railway, avionics and space, autonomous systems, industrial control, etc.
  11. Emerging Technologies
    Techniques for 2.5D/3D ICs, quantum computing architecttures, memristors, spintronics, microfluidics, etc.
  12. Design for Security
    Fault attacks, fault tolerance-based countermeasures, scan-based attacks and countermeasures, hardware trojans, security vs. reliability trade-offs, interaction between VLSI test, trust, and reliability.

Call for Special Sessions

PDF Version

DFT’ seeks proposals for Special Sessions. The special sessions should aim at providing a complementary experience with respect to the regular sessions by focusing on hot and emerging topics of interest to the DFT community, as well as on multi-disciplinary topics, that are expected to have a significant impact on DFT activities in the future (e.g. reliability aspects in Approximate Computing, Quantum Computing, use of COTS Electronics for Space applications). A special session could consist of a set of individual presentations or a panel, possibly with experts from the industry.

Upon acceptance, special session presenters can prepare either a single paper for the entire session or one paper per presenter to be included in the formal proceedings. For this reason, papers (presenting original and unpublished contributions and that may be 4 pages or 6 pages long) for special session will go through review process. For the single-session papers, it will be possible to purchase 2 extra pages at an additional cost. Accepted papers will appear in the formal proceedings of DFT symposium. Proceedings will be published by the IEEE Computer Society and will appear in the Digital Library

Submission Process: Submitted proposals should include:

  • a title of the special session
  • a maximum 250-word abstract outlining the session's scope, topics and relevance for DFT symposium
  • name, contact information and short biography of the organizer(s)
  • format of the session: (1) panel or set of individual presentations, and (2) single paper per session or one paper per presenter
  • list of three/four contributed presentations (including titles, presenter names, contact information of the corresponding presenter, and an abstract of each contribution). For panel proposals, list three to five panelists and their area of expertise.

Proposal submissions should be presented in a single PDF to be sent via e-mail to the Special Session Chair:

  • Kanad Basu - kanad.basu@utdallas.edu
  • email subject: DFT’ Special Session Proposal

By means of their submission, all presenters agree to register for and participate to DFT’, in case their special session proposal is accepted.

Organizing Committee

General Chairs Prashant Joshi Intel, United States prashant.d.joshi@intel.com
Luigi Dilillo LIRMM, France luigi.dilillo@lirmm.fr
Program Chairs Luca Cassano Politecnico di Milano, Italy luca.cassano@polimi.it
Sreejit Chakravarty Intel sreejit.chakravarty@intel.com
Special Session Kanad Basu University of Texas, United States kanad.basu@utdallas.edu
Publicity Pedro Reviriego Universidad Carlos III de Madrid, Spain revirieg@it.uc3m.es
Majed Valad Beigi AMD majed.valadbeigi@amd.com
Industrial Liason Stephan Eggerglues Siemens, Germany stephan_eggersgluess@mentor.com
Sudhanva Gurumurthi AMD sudhanva.gurumurthi@amd.com
Publication Alberto Bosio École Central de Lyon, France alberto.bosio@ec-lyon.fr
Audio/Visual Lucas Matana Luza LIRMM, France lucas.matana-luza@lirmm.fr
Andre Mattos LIRMM, France andre.martins-pio-de-mattos@lirmm.fr
Web Douglas Santos LIRMM, France douglas.almeida-dos-santos@lirmm.fr

Technical Sponsors