Mark M. Tehranipoor is currently the Intel Charles E. Young Preeminence Endowed Chair Professor and the Chair of the Department of Electrical and Computer Engineering (ECE) at the University of Florida. His current research projects include: hardware security and trust, supply chain security, IoT security, VLSI design, test and reliability. He has 21 patents, 18 books, and 500+ conference/journal publications. He is a recipient of 17 best paper awards and nominations, as well as the 2008 IEEE Computer Society (CS) Meritorious Service Award, the 2012 IEEE CS Outstanding Contribution, the 2009 NSF CAREER Award, and the 2014 AFOSR MURI award. He received the 2020 University of Florida Innovation of the year as well as teacher/scholar of the year awards. He co-founded the IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), IEEE International Conference on Physical Assurance and Inspection of Electronics (PAINE). He serves on the program committee of more than a dozen leading conferences and workshops. He has also served as Program and General Chair of a number of IEEE and ACM sponsored conferences and workshops (HOST, ITC, DFT, D3T, DBT, NATW, and more). He is currently serving as a founding EIC for Journal on Hardware and Systems Security (HaSS) and served as Associate Editor for TC, JETTA, JOLPE, TODAES, IEEE D&T, TVLSI. He is currently serving as a founding director for Florida Institute for Cybersecurity Research (FICS) and a number of other centers with focus on microelectronics security. Dr. Tehranipoor is a Fellow of the IEEE, a Fellow of the ACM, a Fellow of the National Academy of Inventors (NAI), a Golden Core Member of IEEE CS, and Member of ACM SIGDA.
Much of the security concerns during the design of modern system on chips (SoCs) or system-in-package (SiPs) have to do with design mistakes, lack of understanding of security vulnerabilities and the many attack surfaces and vectors that exist. This presentation will discuss challenges to securing silicon development lifecycle, makes a case for automation to lower the development cost, offers solutions to engineers and practitioners, and present research challenges and opportunities for academics.
Mauro Pipponzi has worked for more than 35 years in IC design and EDA. His experience covers design and design management of products in a number of application areas such as Consumer, Telecom and Automotive, as well as working on software solutions for testing, synthesis, and functional safety. In 2012 he started working on Functional Safety, in particular developing tools for Functional Safety automation in Yogitech and in Intel. After three years working on tests and reliability, at the beginning of 2023 he returned to Functional Safety after joining SiFive as a Senior Principal Architect.
In 2019 the second edition of the ISO26262 standard for functional safety for vehicles has been released, which included the new part 11 specifically dedicated to interpretation of the standard to semiconductors. Using a RISC V processor as an example we will review how the approach to functional safety has evolved in these past years, the level of analysis, the solutions and the challenges, touching random failure, systematic failure, design environment, relationships to related fields, such as test and reliability.
Dr. Pierre Maillard joined AMD’s Adaptive Embedded Computing Group (AECG) in 2013, where he is currently leading the Radiation Effects & RAS solution team. The team focuses on the architecture, development, and validation of commercial and rad. tolerant FPGA/ACAP solutions, for the Terrestrial (Telecom, Avionics, Automotive, Datacenter, AI, etc.) and Space markets. He is a Senior Member of IEEE and has over 20 presentations and publications in industry-leading conferences and journals. He holds over 20 issued patents in the field of radiation effects on electronics. He received his B.S. in Electrical Engineering (EE) from the University of Montpellier II and his M.S. and Ph.D. in EE from Vanderbilt University.
This keynote talk covers Radiation Effects in Field Programmable Gate Arrays (FPGAs) and Systems on Chips (SoCs). The ability to implement complex designs and evolving algorithms in reconfigurable devices makes FPGAs attractive for many Terrestrial and Space applications, compared to fixed function Application Specific Integrated Circuits (ASICs). This talk will address the basics of SRAM and non-volatile-based FPGA architecture and their evolution to modern/complex SoCs and Adaptive Compute Acceleration Platform (ACAP) devices. Then we will discuss Single Event Effects (SEE) and Total Ionizing Dose (TID) mechanisms, errors classification, mitigation, test methodologies, and representative results. The final section will focus on challenges and potential paths to address requirements for next-gen Terrestrial (telecom, automotive, data centers, avionics, etc.), defense, and space markets.