Dr. Dan Stanzione, Associate Vice President for Research at The University of Texas at Austin since 2018 and Executive Director of the Texas Advanced Computing Center (TACC) since 2014, is a nationally recognized leader in high performance computing. He is the principal investigator (PI) for a National Science Foundation (NSF) grant to deploy Frontera, which is the fastest supercomputer at any U.S. university. Stanzione is also the PI of TACC's Stampede2 and Wrangler systems, supercomputers for high performance computing and for data-focused applications, respectively. For six years he was co-PI of CyVerse, a large-scale NSF life sciences cyberinfrastructure. Stanzione was also a co-PI for TACC's Ranger and Lonestar supercomputers, large-scale NSF systems previously deployed at UT Austin. Stanzione received his bachelor's degree in electrical engineering and his master's degree and doctorate in computer engineering from Clemson University.
Ramesh Karri is a Professor of Electrical and Computer Engineering at New York University. He co-directs the NYU Center for Cyber Security (http://cyber.nyu.edu). He co-founded the Trust-Hub (http://trust-hub.org) and organizes the Embedded Systems Challenge (https://csaw.engineering.nyu.edu/esc), the annual red team blue team event. Ramesh Karri has a Ph.D. in Computer Science and Engineering, from the University of California at San Diego and a B.E in ECE from Andhra University. His research and education activities in hardware cybersecurity include trustworthy integrated circuits, processors and cyber-physical systems; security-aware computer-aided design, test, verification, validation, and reliability; hardware security competitions, benchmarks and metrics; biochip security; additive manufacturing security. He has published over 300 articles in leading journals and conference proceedings.
Ramesh Karri's work in trustworthy hardware received best paper award nominations (ICCD 2015 and DFTS 2015), awards (ACM TODAES 2017, ITC 2014, CCS 2013, DFTS 2013 and VLSI Design 2012, ACM Student Research Competition at DAC 2012, ICCAD 2013, DAC 2014, ACM Grand Finals 2013, Kaspersky Challenge and Embedded Security Challenge). He received the Humboldt Fellowship and the National Science Foundation CAREER Award. He is a Fellow of the IEEE for his contributions to and leadership in Trustworthy Hardware. He is the Editor-in-Chief of ACM Journal of Emerging Technologies in Computing. Besides, he served/s as the Associate Editor of IEEE Transactions on Information Forensics and Security (2010-2014), IEEE Transactions on CAD (2014-), ACM Journal of Emerging Computing Technologies (2007-), ACM Transactions on Design Automation of Electronic Systems (2014-), IEEE Access (2015-), IEEE Transactions on Emerging Technologies in Computing (2015-), IEEE Design and Test (2015-) and IEEE Embedded Systems Letters (2016-). He served as an IEEE Computer Society Distinguished Visitor (2013-2015). He served on the Executive Committee of the IEEE/ACM Design Automation Conference leading the Security@DAC initiative (2014-2017). He has given keynotes, talks, and tutorials on Hardware Security and Trust.
Integrated Circuit (IC) designers use third-party intellectual property (IP) cores in their designs. Further, they outsource the various steps in the IC design, manufacturing, testing and packaging flow. Such a globally distributed electronics supply chain is introducing security vulnerabilities in the ICs and the systems that use them. This is forcing IC designers and end-users to re-evaluate their trust in ICs. If an attacker gets hold of an unprotected IC, he can reverse engineer the IC and pirate the IP. Similarly, she can insert malicious circuits and backdoors into the IC.
In this talk I will outline High-Level Design for Trust techniques to prevent these and similar attacks: Locking/Obfuscation/Redaction and Secure Sourcing of IPs for High-Level Integration. Locking/Obfuscation implements a built-in obfuscation mechanism in ICs to prevent reverse engineering. Secure sourcing can thwart Trojan insertion in 3rd party Intellectual Properties. I will wrap up the presentation by pointing out why hardware security is an essential objective from economics, security, and safety aspects and offer my vision of the developing field of hardware cybersecurity.
Riccardo Locatelli received the Laurea degree (summa cum laude) in electronic engineering, and the related PhD degree from the University of Pisa, Italy, in 2000 and 2004, respectively. In 1999, he was a research intern with the Microelectronics Section of the European Space Agency, The Netherlands and in 2003 visiting researcher at the Advanced System Technology Laboratory of STMicroelectronics, France. From 2000 to 2002 he worked as digital designer for video and VDSL architectures at Pisa University Electronic Department. From 2004 to 2017, he has been pioneering the Network on Chip concept and technology as main architect and team manager with STMicroelectronics, Grenoble, France, designing and introducing ST proprietary NoC solution into several chips. Since 2017 he is with Intel Corporation managing the deployment of Functional Safety features across current and future IPs and SoCs for IOT Group markets. He has published more than 30 papers in international journals and conference proceedings and he is the coauthor of a book. He has filed around 20 international patents on NoC and safety. He has been invited professor at Grenoble, Pisa and Bologna University.
Edge applications for autonomous systems require high performance computation and augmented dependability. Silicon integrity is a key asset in this context and combined with system level ingredients it enables efficient HW/SW safety architectures.
This talk will present the safety architecture technologies and discuss the silicon integrity capabilities and features. Challenges and future main research directions will be presented.