The updated program for DFTS, containing room numbers and updated timeline can be found here .
Preliminary Program
Tuesday, Oct 3
09:00
Opening Session
09:20
Secure SoC Development Lifecycle: Challenges and Solutions
Speaker: Prof. Mark M. Tehranipoor
10:20 - 10:50: Coffee Break (Sponsor)
Session Chair: Matteo Sonza Reorda
10:50
Fault Secured JPEG-Codec Hardware Accelerator with Piracy Detective Control using Secure Fingerprint Template.
Rahul Chaurasia, Abhinav Reddy Asireddy and Anirban Sengupta.
11:10
EnSAFe: Enabling Sustainable SoC Security Auditing using eFPGA-based Accelerators.
Mridha Md Mashahedur Rahman, Shams Tarek, Kimia Zamiri Azar and Farimah Farahmandi.
11:30
Improving the Detection of Hardware Trojan Horses in Microprocessors via Hamming Codes.
Alessandro Palumbo, Luca Cassano, Pedro Reviriego and Marco Ottavi.
11:50
Built-in Software Obfuscation for Protecting Microprocessors against Hardware Trojan Horses.
Alessandro Palumbo, Marco Ottavi and Luca Cassano. (SHORT PRESENTATION)
12:00
On Attacking Scan-based Logic Locking Schemes.
Govind Rajhans Jadhav, Sonali Shukla and Virendra Singh.(SHORT PRESENTATION)
12:10
An Efficient Security Closure Methodology for EM-based Attacks on Power Grid Structures.
Alexandra Takou, Pavlos Stoikos, Moysis Moysis, George Floros, Nestor Evmorfopoulos and Georgios Stamoulis. (SHORT PRESENTATION)
12:20
A Self Aware Security Approach for Real Time Neural Network Applications from Row Hammer Attacks in Multi FPGA Multi User Environment.
Krishnendu Guha and Gouriprasad Bhattacharyya.(SHORT PRESENTATION)
12:30 - 14:00: Lunch
Session Chair: Athanasios Papadimitriou
14:00
An Evaluation of a Testability Measure for State Assignment to Estimate Transition Fault Coverage for Controllers.
Toshinori Hosokawa, Kyohei Iizuka and Masayoshi Yoshimura.
14:20
A Block Partitioning Method for Region Exhaustive Test to Reduce the Number of Test Patterns and to Improve Gate Exhaustive Fault Coverage.
Momona Mizota, Toshinori Hosokawa, Masayoshi Yoshimura and Masayuki Arai.
14:40
Evaluating the Impact of Aging on Path-Delay Self-Test Libraries.
Lorena Anghel, Riccardo Cantoro, Michele Portolan, Sandro Sartoni and Matteo Sonza Reorda.
15:00
An Evaluation of Estimated Field Random Testability for Data Paths at Register Transfer Level Using Status Signal Sequences Based on k-Consecutive State Transitions for Field Testing.
Yudai Toyooka, Haruki Watanabe, Toshinori Hosokawa and Masayoshi Yoshimura. (SHORT PRESENTATION)
15:10
Black-Box IP Validation with the SafeTI Traffic Injector: A Success Story.
Francisco Fuentes, Sergi Alcaide, Raimon Casanova and Jaume Abella. (SHORT PRESENTATION)
15:20
Partial Triple Modular Redundancy (TMR) Method for Fault-Tolerant Circuit based on HITS Algorithm.
Yu Xie, Wen-Yue Yu, Ning Zhang, He Chen and Yi-Zhuang Xie (SHORT PRESENTATION)
15:30
Gradient Descent Iterative Correction Unit for Fixed Point Parity Based Codes.
Oana Boncalo and Alexandru Amaricai. (SHORT PRESENTATION)
15:40 - 16:10: Coffee Break (Sponsor)
Session Chair: Haralampos Stratigopoulos
16:10
Analyzing the Reliability of Alternative Convolution Implementations for Deep Learning Applications.
Cristiana Bolchini, Luca Cassano, Antonio Miele, Alessandro Nazzari and Dario Passarello.
16:30
Uncovering hidden vulnerabilities in DNNs through evolutionary-based Image Test Libraries.
Vittorio Turco, Annachiara Ruospo, Gabriele Gavarini, Ernesto Sanchez and Matteo Sonza Reorda.
16:50
Investigating the effect of approximate multipliers on the resilience of a systolic array DNN accelerator.
Salvatore Pappalardo, Ali Piri, Annachiara Ruospo, Ian O'Connor, Bastien Deveautour, Alberto Bosio and Ernesto Sanchez.
17:10
Analysis and Improvement of Resilience for Long Short-Term Memory Neural Networks.
Mohammad Hasan Ahmadilivani, Jaan Raik, Masoud Daneshtalab and Alar Kuusik. (SHORT PRESENTATION)
Highly Efficient Layered Syndrome-based Double Error Correction Utilizing Current Summing in RRAM Cells to Simplify Decoder
Shruti Dutta, Sai Charan Rachamadugu Chinni, Abhishek Das and Nur Touba.
11:10
DDSR: An Online GPGPU Instruction Decoder Error Detecting and Correcting Architecture.
Raghunandana K K, Yogesh Prasad K R, Matteo Sonza Reorda and Virendra Singh.
11:30
Image Degradation in Time Due to Interacting Hot Pixels.
Glenn Chapman, Li-Yu Wu, Israel Koren, Zahava Koren and Klinsmann J. Coelho Silva Menes.
11:50
An Estimation Method of Defect Types Using Artificial Neural Networks and Fault Detection Information.
Natsuki Ota, Toshinori Hosokawa, Koji Yamazaki, Yukari Yamauchi and Masayuki Arai.
12:10
An efficient High-Volume Production Performance Screening using On-Chip Ring Oscillators.
Tobias Kilian, Abhishek Sengupta, Daniel Tille, Martin Huch and Ulf Schlichtmann.
12:30 - 14:00: Lunch
Safety and Security Assessment through X-Ray Illumination
Session Chair: Paolo Maistri
14:15
Soft-SoC Robustness Evaluation using X-Rays: a Case Study and Differences with other Beams
14:30
X ray nanoprobe for fault attacks and circuit edits on 28-nm integrated circuits
14:45
Simulation Methodology for Assessing X-Ray Effects on Digital Circuits
Reliability of Microcontrollers in Radiation Harsh Environment at Different Levels of Abstraction. The Case Study of the HARV RISC-V SoC
Session Chair: Luigi Dilillo
15:00
Characterization of a Fault-Tolerant RISC-V System-on-Chip for Space Environments
15:20
Implementation and Reliability Evaluation of a Vector Extension for a RISC-V System-on-Chip
15:40
Hardening a Real-Time Operating System for a Dependable RISC-V System-on-Chip
Towards AI-based cross-layer resilience: from reliability estimation at design phase to in-field error detection and on-chip sensor data processing
Session Chair: Mihalis Psarakis
14:00
Challenges in Machine Learning Techniques to Estimate Reliability from Transistors to Circuits
14:20
On-Chip Sensors Data Collection and Analysis for SoC Health Management
14:40
A Machine Learning-driven EDAC Method for Space-Application Memory
Resilience of Brain-Inspired Applications: Test and Reliability for Modern ML and AI Hardware Implementations
Session Chairs: Elena-Ioana Vatajelu and Ernesto Sanchez
15:00
Testing and Reliability of Spiking Neural Networks: A Review of the State-of-the-Art
15:20
On the resilience of representative and novel data formats in CNNs
15:40
Fault tolerance of memristor-based neural networks: a comparative study between formal and spiking neural networks
16:00 - 19:00: Social Event (TBC): visit of Juan Les Pins
19:00 - 20:30: Gala Cocktail (Sponsor)
20:30 - 23:30: Gala Dinner (Sponsor)
Thursday, Oct 5
09:00
State of the Art of Functional Safety in 2023
Speaker: Dr. Mauro Pipponzi
10:20 - 10:50: Coffee Break (Sponsor)
Session Chair: Paolo Maistri
10:50
Neutron Radiation Tests of the NEORV32 RISC-V SoC on Flash-Based FPGAs.
Kevin Böhmer, Bruno Forlin, Carlo Cazzaniga, Paolo Rech, Gianluca Furano, Nikolaos Alachiotis and Marco Ottavi.
11:10
Accurate Soft Error Rate Evaluation Using Event-Driven Dynamic Timing Analysis.
Georgios-Ioannis Paliaroutis, Pelopidas Tsoumanis, Dimitrios Garyfallou, Anastasis Vagenas, Nestor Evmorfopoulos and George Stamoulis.
11:30
Towards a Comprehensive SET Analysis Flow for VLSI Circuits using Static Timing Analysis.
Christos Georgakidis, Dimitris Valiantzas, Stavros Simoglou, Iordanis Lilitsis, Nikolaos Chatzivangelis, Marko Andjelkovic, Christos Sotiriou and Milos Krstic.
11:50
On the Prediction of Hardware Security Properties of HLS Designs Using Graph Neural Networks.
Amalia-Artemis Koufopoulou, Athanasios Papadimitriou, Aggelos Pikrakis, Mihalis Psarakis and David Hely.
12:10
QuardTropy: Detecting and Quantifying Unauthorized Information Leakage in Hardware Designs using g-entropy.
Hasan Al-Shaikh, Mohammad Bin Monjil, Kimia Zamiri Azar, Farimah Farahmandi, Mark Tehranipoor and Fahim Rahman.
12:30 - 14:00: Lunch
Session Chair: Ernesto Sanchez
14:00
SASL-JTAG: A Light-Weight Dependable JTAG.
Senling Wang, Shaoqi Wei, Jun Ma, Hiroshi Kai, Yoshinobu Higami, Hiroshi Takahashi, Akihiro Shimizu, Xiaoqing Wen and Tianming Ni.
14:20
A Low-Cost Hardware Accelerator for CCSDS 123 Lossless Hyperspectral Image Compression.
Wesley Grignani, Douglas Santos, Luigi Dilillo, Felipe Viel and Douglas Melo.
14:40
RC-IJTAG: A Methodology for Designing Remotely-Controlled IEEE 1687 Scan Networks.
Payam Habiby, Sebastian Huhn and Rolf Drechsler.
15:00
Iterative Mitigation of Insecure Resource Sharing Produced by High-level Synthesis.
Zahin Ibnat, Hadi Mardani Kamali and Farimah Farahmandi.
15:20
Exploration of System-on-Chip Secure-Boot Vulnerability to Fault-Injection by Side-Channel Analysis.
Clément Fanjas, Aboulkassimi Driss, Jessy Clédière and Simon Pontié.
15:40 - 16:10: Coffee Break (Sponsor)
Testing, Reliability, and Hardware Security of Computing-in Memories
Session Chair: Jin-Fu Li
16:10
Testing of Computing-In Memories: Faults, Test Algorithms, and Design-for-Testability
16:30
Reliability of Computing-In-Memories: Threats, Detection Methods, and Mitigation Approaches
16:50
Hardware Trojans of Computing-In-Memories: Issues and Methods