Technical Program @ DFT 2018

Monday, October 8, 2018

08:00-09:00am Registration & breakfast

09:00-10:00am Keynote #1: "Redundancy & Testability Hit the Road for Resilient
                                                  Autonomous Driving"
                                                  Dr. Nirmal R. Saxena, NVIDIA
                                                  Abstract and bio are available here

10:00-10:30am Coffee Break

10:30-12:00pm Session 1 - Memories

Complementary Resistive Switch Sensing (Best Paper Award Nominee)

Danilo Pellegrini, Marco Ottavi, Eugenio Martinelli and Corrado Di Natale

Physics-Informed Machine Learning for DRAM Error Modeling

Elisabeth Baseman, Nathan Debardeleben, Sean Blanchard, Juston Moore, Olena Tkachenko, Kurt Ferreira, Taniya Siddiqua and Vilas Sridharan

Construction of latch design with complete double node upset tolerant capability using C-element

Yuta Yamamoto and Kazuteru Namba

12:00pm-01:00pm Lunch Break

01:00-02:30pm Session 2 - Testing

Improving the Resolution of Multiple Defect Diagnosis by Removing and Selecting Tests (Best Paper Award Nominee)

Naixing Wang, Irith Pomeranz, Brady Benware, Enamul Amyeen and Srikanth Venkataraman

A Method to Model Statistical Path Delays for Accurate Defect Coverage

Pavan Kumar Javvaji and Spyros Tragoudas

Investigation of Mean-Error Metrics for Testing Approximate Integrated Circuits

Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi and Alberto Bosio

02:30-03:00pm Coffee Break

03:00-04:00pm Invited Talk #1: "Are System Level Tests Unavoidable for High End
                                                        Adit Singh, Auburn University

04:00-05:00pm Session 3 - Devices and Testing (Short Presentations)

FPGA SEE Test with Ultra-High Energy Heavy Ions

Gianluca Furano, Antonis Tavoularis, Lucana Santos, Veronique Ferlet-Cavrois, Cesar Boatella, Ruben Garcia Alia, Pablo Fernandez Martinez, Maria Kastriotou, Vanessa Wyrwoll, Salvatore Danzeca, Maris Tali, Dejan Gacnik, Iztok Kramberger, Konstantinos Maragos and George Lentaris

Detecting and Characterizing Soft Errors (SEUs) with Digital Imager Pixels down to 1.2 um

Glenn Chapman, Rohan Thomas, Klinsmann Joel J. Coelho Silva Meneses, Israel Koren and Zahava Koren

MATS**: An On-Line Testing Approach for Reconfigurable Embedded Memories

Luca Sterpone and Ludovica Bozzoli

45 nm Bit-Interleaving Differential 10T Low Leakage FinFET Based SRAM with Column-Wise Write Access Control

Vishal Gupta, Saurabh Khandelwal, Jimson Mathew and Marco Ottavi

Tuesday, October 9, 2018

09:00-10:00am Keynote #2: "Supercomputer Reliability - Actionable Insights from
                                                   Neutrons, Data Analytics, and Field Data"
                                                    Dr. Nathan DeBardeleben, Los Alamos National Laboratory
                                                    Abstract and bio are available here

10:00-10:30am Coffee Break

10:30-12:00pm Session 4 - Programmable Logic & CMOS technologies

Threshold Voltage Extraction Using Static NBTI Aging

Puneet Savanur and Spyros Tragoudas

Effects of Voltage and Temperature Variations on the Electrical Masking Capability of Sub-65 nm Combinational Logic Circuits

Semiu Olowogemo, William Robinson and Daniel Limbrick

A Placement-aware Soft Error Rate Estimation of Combinational Circuits for Multiple Transient Faults in CMOS Technology

Georgios Ioannis Paliaroutis, Pelopidas Tsoumanis, Nestor Evmorfopoulos, George Dimitriou and Georgios Stamoulis

12:00pm-01:30pm Lunch Break

01:30-02:30pm Invited Talk #2: "Detecting and counteracting benign faults
                                                        and malicious attacks in cyber physical systems"
                                                        Dr. Israel Koren, University of Massachusetts at Amherst

02:30pm-03:00pm Coffee Break

03:00-04:30pm Session 5 - Aging & Test

Performance-based and Aging-aware Resource Allocation for Concurrent GPU Applications

Zois-Gerasimos Tasoulas, Ryan Guss and Iraklis Anagnostopoulos

Multiple Fault Detection in Nano Programmable Logic Arrays

Fabrizio Lombardi and Pilin Junsangsri

Analysis of the Effects of Single Event Upsets (SEUs) on User Memory in FPGA Implemented Viterbi Decoders

Zhen Gao, Lina Yan, Jinhua Zhu, Ruishi Han and Pedro Reviriego

04:30-05:15pm Panel: Radiation Effects
Panelists:     Dr. Cheryl Lam (Sandia National Lab)
                     Dr. Adam Watkins (Blue Origin)
                     Dr. Nathan DeBardeleben (Los Alamos National Labs)
                     Dr. Marco Rovatti (European Space Agency)

05:15pm-06:00pm Reception

06:00pm-09:00pm Banquet

Wednesday, October 10, 2018

09:00-10:00am Session 6 - System Level Techniques (Short Presentations)

Evaluating the Resilience of Parallel Applications

Mark Wilkening, Fritz Previlon, David Kaeli, Sudhanva Gurumurthi, Steven Raasch and Vilas Sridharan

State Recovery for Coarse-Grain TMR Designs in FPGAs Using Partial Reconfiguration

Markus Sch├╝tz, Andreas Steininger, Florian Huemer and Jakob Lechner

Hybrid on-line self-test strategy for dual-core lockstep processors

Andrea Floridia and Ernesto Sanchez

Postprocessing Procedure for Reducing the Faulty Switching Activity of a Low-Power Test Set

Irith Pomeranz

10:00-10:15am Coffee Break

10:15am-11:45am Session 7 - Networks, Coding, and Security

Efficient Non-binary Hamming Codes for Limited Magnitude Errors in MLC PCMs (Best Paper Award Nominee)

Abhishek Das and Nur A. Touba

A Runtime Fault-Tolerant Routing Scheme for Partially Connected 3D Networks-On-Chip

Alexandre Coelho, Amir Charif, Nacer-Eddine Zergainoh and Raoul Velazco

Fast Dynamic Device Authentication Based on Lorenz Chaotic Systems

Lake Bu, Cheng Hai and Michel Kinsy

11:45-12:00pm Closing Remarks and Best Paper Award Presentation