IEEE Int. Symposium on Defect and Fault Tolerance
 in VLSI and Nanotechnology Systems
 IEEE Int. Symposium on Defect and Fault Tolerance
 in VLSI and Nanotechnology Systems

Preliminary technical program

(L) Long Paper
(S) Short Paper
Best Paper Candidate
Best Student Paper Candidate

Monday, October 23, 2017

08:00-09:00am Registration

09:00-09:20am Conference Opening

09:20-10:20am Keynote Talk 1: "Murphy Goes 3D"
                                    by Erik Jan Marinissen - IMEC, Belgium
                                    Abstract and bio are available here

10:20-10:30am Coffee Break

10:30-11:40am Session 1 - Test and Reliability in Memories


(L) Lifetime Memory Reliability Data from the Field

Taniya Siddiqua, Vilas Sridharan, Steven Raasch, Nathan Debardeleben, Kurt Ferreira, Scott Levy, Elisabeth Baseman and Qiang Guan

(L) High-Yield Design of High Density SRAM for Low-Voltage and Low-Leakage Operations

Dhori Kedar Janardan, Lorenzo Ciampolini, Hitesh Chawla, Ashish Kumar, Pashant Pandey, Promod Kumar, Florian Cacho and Damien Croain

(L) Investigating the Effects of Process Variations and System Workloads on Endurance of Non-Volatile Caches

Amir Mahdi Hosseini Monazzah, Hamed Farbeh and Seyed Ghassem Miremadi

(S) Towards SRAM Leakage Power Minimization by Aggressive Standby Voltage Scaling – Experiments on 40nm Test Chips

Xin Fan, Jan Stuijt and Tobias Gemmeke

11:40-12:30pm Session 2 - Security


(L) RASSS: A Perfidy-Aware Protocol for Designing Trustworthy Distributed Systems

Lake Bu, Hien D. Nguyen and Michel A. Kinsy

(L) Realizing Strong PUF from Weak PUF via Neural Computing

Leandro Santiago, Vinay C Patil, Sandip Kundu, Felipe M. G. Fraça, Charles B. Prado, Tiago A. O. Alves and Leandro A. J. Marzulo

(S) Preventing Scan-Based Side-Channel Attacks Through Key Masking

Satyadev Ahlawat, Darshit Vaghani and Virendra Singh

12:30pm-01:50pm Lunch Break

01:50-02:50pm Session 3 - Special Session on Hardware and Software Innovations in Energy-Efficient
                                                             System-Reliability Monitoring

Vasileios Tenentes, Geoff Merrett and Bashir M. Al-Hashimi (University of Southampton)

Vasileios Tenentes (University of Southampton)

(L) Reliable and energy-efficient guardbands for ageing

Hussam Amrouch and Jörg Henkel

(L) Genetic Algorithms and Sensors for Exploring System Power Integrity

Shidhartha Das

(L) Runtime Learning for Fault-Tolerant and Energy-Efficient Systems

Charles Leech and Graeme M. Bragg

02:50-03:00pm Coffee Break

03:00-04:00pm Session 4 - Approximate and Stochastic Circuits


(L) Eliminating a Hidden Error Source in Stochastic Circuits

Paishun Ting and John Hayes

(L) Simulation-Based Evaluation of Frequency Upscaled Operation of Exact/Approximate Ripple Carry Adders

Thulasiraman Nandhakumar, Huang Junqi, Haider Almurib and Fabrizio Lombardi

(L) CAL: Exploring Cost, Accuracy, and Latency in Approximate and Speculative Adder Design

Sina Boroumand, Hadi P. Afshar, Philip Brisk and Siamak Mohammadi

04:00-05:00pm Demo session

05:00-06:00pm TPC meeting

Tuesday, October 24, 2017

08:00-09:00am Registration

09:00-10:00am Keynote Talk 2: "Hardware-Assisted Security: Promises, Pitfalls and Opportunities"
                                    by Prof. Ahmad-Reza Sadeghi - TU Darmstadt, Germany
                                    Abstract and bio are available here

10:00-10:15am Coffee Break

10:15-11:15am Session 5 - Reliability Strategies for Multicores, GPUs and Networks


(L) Kernel Vulnerability Factor and Efficient Hardening for Histogram of Oriented Gradients

Lucas Fernando Weigel, Fernando Fernandes Dos Santos, Philippe Olivier Alexandre Navaux and Paolo Rech

(L) A Dynamic Reliability Management Framework for Heterogeneous Multicore Systems

Alessandro Baldassari, Cristiana Bolchini and Antonio Miele

(S) A scrubbing scheduling approach for reliable FPGA multicore processors with real-time constraints

Mihalis Psarakis and Aitzan Sari

(S) Region Based Containers - A new paradigm for the analysis of Fault Tolerant Networks

Prashant D. Joshi, D. F. Hsu, Arun Sen, Said Hamdioui and Koen Bertels

11:15-12:15pm Session 6 - Error Detection and Software-based Self-Test


(L) On-Line Software-based Self-Test for ECC of Embedded RAM Memories

Marco Restifo, Paolo Bernardi, Alessandro Sansonetti and Sergio De Luca

(L) On the Optimization of SBST Test Program Compaction

Riccardo Cantoro, Ernesto Sanchez, Matteo Sonza Reorda, Giovanni Squillero and Emanuele Valea

(S) Low Cost Error Monitoring for Improved Maintainability of IoT Applications

Mauricio D. Gutierrez, Vasileios Tenentes, Daniele Rossi and Tom Kazmierski

(S) A Defective Level Monitor of Open Defects in 3D ICs with a Comparator of Offset Cancellation Type

Michiya Kanda, Masaki Hashizume, Hiroyuki Yotsuyanagi and Shyue-Kung Lu

12:15pm-01:05pm Lunch Break

01:05-01:50pm Keynote Talk 3: "Fault-Tolerant Microbiology-on-a-Chip: Defects, Testing, Fault Avoidance, and Error
                                    Recovery in Microfluidic Biochips"
                                    by Prof. Krishnendu Chakrabarty - Duke University, US
                                    Abstract and bio are available here

01:50-03:00pm Session 7 - Special Session on Fault-Tolerant Microbiology-on-a-Chip: Defects, Testing, Fault
                                                             Avoidance, and Error Recovery in Microfluidic Biochips

Krishnendu Chakrabarty (Duke University)

Krishnendu Chakrabarty (Duke University)

(L) Volume Management for Fault-tolerant Continuous-flow Microfluidics

Alexander Schneider, Paul Pop and Jan Madsen

(L) Design-for-Testability for Paper-based Digital Microfluidic Biochips

Jian-De Li, Sying-Jyan Wang, Katherine Shu-Min Li and Tsung-Yi Ho

(L) Reliability-aware Synthesis and Fault Test of Fully Programmable Valve Arrays (FPVAs)

Bing Li and Ulf Schlichtmann

(S) A Scalable Pseudo-Exhaustive Search for Fault Diagnosis in Microfluidic Biochips

Gokulkrishnan V, Kamakoti Veezhinathan, Nitin Chandrachoodan and Seetal Potluri

03:45pm Social Event: Guided punting trip on the River Cam

06:30pm Social Dinner at the Trinity College

Wednesday, October 25, 2017

08:00-09:00am Registration

09:00-10:00am Keynote Talk 4: "Functional Safety and Security: the Challenges in Developing IP for These Markets"
                                    by Pete Harrod - ARM, UK
                                    Abstract and bio are available here

10:00-10:40am Demo Session

10:40-11:30am Session 8 - Aging Analysis


(L) Early estimation of aging in the design flow of integrated circuits through a programmable hardware module

Chiara Sandionigi, Mauricio Altieri and Olivier Heron

(L) Lifetime Reliability Characterization of N/MEMS Used in Power Gating of Digital Integrated Circuits

Haider Alrudainy, Rishad Shafik, Andrey Mokhov and Alex Yakovlev

(S) Unintrusive Aging Analysis based on Offline Learning

Pedro Fausto Rodrigues Leite Junior, Frank Sill Torres and Rolf Drechsler

11:30-12:20pm Session 9 - Characterization and Fault Tolerance for SEUs


(L) REMORA: A Hybrid Low-Cost Soft-Error Reliable Fault Tolerant Architecture

Shoba Gopalakrishnan and Virendra Singh

(S) Scheduling Voter Checks to Detect Configuration Memory Errors in FPGA-based TMR Systems

Nguyen T. H. Nguyen, Ediz Cetin and Oliver Diessel

(S) High-energy Neutrons Characterization of a Safety Critical Computing System

Andrea Fedi, Marco Ottavi, Antimo Bruno, Carlo Cazzaniga, Gianluca Furano, Roberto Senesi and Carla Andreani

(S) Exploring Soft Errors (SEUs) with Digital Imager Pixels ranging from 7 um to 1.2 um

Glenn Chapman, Israel Koren, Zahava Koren, Parham Pourbakht and Peter Le

12:20pm-02:00pm Lunch Break

02:00-02:40pm Session 10 - Architectural Approaches for Reliability


(S) Detecting Errors in Instructions with Bloom Filters

Mert Atamaner, Oguz Ergin, Marco Ottavi and Pedro Reviriego Vasallo

(S) High Performance Fault Tolerance Through Predictive Instruction Re-Execution

Jyothish Soman and Timothy Jones

(S) A Resilient Scheduler for Dataflow Execution

Tiago Alves, Leandro A. J. Marzulo, Felipe M. G. França and Sandip Kundu

(S) A Novel Low-Overhead Fault Tolerant Parallel-Pipelined FFT Design

Yu Xie, Chen Yang, Chuang-An Mao, He Chen and Yi-Zhuang Xie

02:40-03:30pm Demo session

03:30-04:40pm Session 11 - Test Generation and Test Data Volume


(L) Reconfigurable TAP Controllers with Embedded Compression for Large Test Data Volume

Sebastian Huhn, Stephan Eggersgluess and Rolf Drechsler

(L) A Dynamic Test Compaction Method on Low Power Test Generation Based on Capture Safe Test Vectors

Toshinori Hosokawa, Atsushi Hirai, Hiroshi Yamazaki and Masayuki Arai

(L) Machine Learning Based Test Pattern Analysis for Localizing Critical Power Activity Areas

Harshad Dhotre, Stephan Eggersgluess, Mehdi Dehbashi, Ulrike Pfannkuchen and Rolf Drechsler

(S) Improving Test Compression with Multiple-Polynomial LFSRs

Yu-Wei Lee and Nur Touba

04:40-04:50pm Conference closing