Preliminary Technical Program

Wednesday October 1, 2014

08:00-09:00 Registration

09:00-09:15 Conference opening

09:15-10:00 Keynote Talk: "Tackling Parameter Variation from an Architectural Perspective"
                       Josep Torrellas, Univ. of Illinois -- Urbana-Champaign

10:00-10:20 Coffee Break

10:20-11:20 Session 1 - Memories

Cecilia Metra, Università di Bologna

Triggering Trojans in SRAM Circuits with X-Propagation

Senwen Kan and Jennifer Dworak

Characterization of Data Retention Faults in DRAM Devices

Angelo Bacchini, Marco Rovatti, Gianluca Furano and Marco Ottavi

Characterizing Soft Error Vulnerability of Cache Coherence Protocols for Chip-Multiprocessors

Chuanlei Zheng and Shuai Wang

11:20- 11:30 Short break

11:30 - 12:30 Session 2 - Self testing

Maria Michael, University of Cyprus

Power Droop Reduction During Logic BIST of Sequential ICs with Launch-On-Shift Scan

Martin Omana, Daniele Rossi, Edda Beniamino, Cecilia Metra, Chandra Tirumurti and Rajesh Galivanche

Diagnostic Self-Test for Dynamically Scheduled Superscalar Processors based on Reconfiguration Techniques for Handling Hard Faults

Mario Schölzel, Tobias Koal and Heinrich T. Vierhaus

Exploration of System Availability During Software-Based Self-Testing in Many-core Systems under Test Latency Constraints

Michael Skitsas, Chrysostomos Nicopoulos and Maria Michael

12:30- 2:00 Lunch Break

2:00- 3:20 Session 3 - Security and Fault Tolerance

Prashant Joshi,

Protecting Cryptographic Hardware against Malicious Attacks by Nonlinear Robust codes

Victor Tomashevich, Yaara Neumeier, Raghavan Kumar, Osnat Keren and Ilia Polian

CSST: Preventing Distribution of Unlicensed and Rejected ICs by Untrusted Foundry and Assembly

Md. Tauhidur Rahman, Domenic Forte, Qihang Shi, Gustavo Contreras and Mohammad Tehranipoor

Reusing DfT Infrastructure For Online Security Monitoring of Systems-on-Chip

Jerry Backer, David Hély and Ramesh Karri

Security Methods in Fault Tolerant Modified Line Graph based

Prashant Joshi and Said Hamdioui

3:20 - 3:50 Coffee Break & Poster Session I

3:50 - 5:30 Session 4 - Emerging technologies

Glenn Chapman, Simon Fraser University

A System-level Scheme for Resistance Drift Tolerance of a Multilevel Phase Change Memory

Fabrizio Lombardi, Jie Han and Pilin Junsangsri

Designs and Analysis of Non-Volatile Memory Cells for Single Event Upset (SEU) Tolerance

Fabrizio Lombardi, Wei Wei and Kazuteru Namba

Reliability Estimation at Block-Level Granularity of Spin-Transfer-Torque MRAMs

Marco Indaco, Elena Vatajelu, Stefano Di Carlo, Paolo Prinetto, Rosa Rodriguez-Montanes and Joan Figueras

Oxide based Resistive RAM: ON/OFF Resistance Analysis versus Circuit Variability

Hassen Aziza, Haithem Ayari, Santhosh Onkaraiah, Mathieu Moreau, Jean-Michel Portal and Marc Bocquet

Using Memristor State Change Behavior to Identify Faults in Photovoltaic Arrays

Jimson Mathew, Yuanfan Yang, Marco Ottavi and Dhiraj K Pradhan

Thursday October 2, 2014

08:00-09:00 Registration

09:00-10:00 Keynote Talk: "Quo Vadis Diagnosis: A Systems View"
                       Neeraj Suri, TU Darmstadt -- Darmstadt

10:00-10:20 Coffee Break

10:20-11:20 Session 5 - Network on Chip

Cristiana Bolchini, Politecnico di Milano

TSV-to-TSV Inductive Coupling-Aware Coding Scheme for 3D Network-on-Chip

Ashkan Eghbal, Pooria Yaghini, Siavash S. Yazdi and Nader Bagherzadeh

Rescuing Healthy Cores Against Disabled Routers

Masoumeh Ebrahimi, Wang Junshi, Letian Huang, Masoud Daneshtalab and Axel Jantsch

A Non-minimal Turn Model for Fault Tolerant and Highly Adaptive Routing in 2D NoCs

Manoj Kumar, Vijay Laxmi, Manoj Gaur, Masoud Daneshtalab, Masoumeh Ebrahimi and Mark Zwolinski

11:20-11:30 Short Break

11:30-12:30 Session 6 - Sensors

Fabrizio Lombardi, Northeastern University

Performance Sensor for Tolerance and Predictive Detection of Delay-Faults

Jorge Semião, André Romão, David Saraiva, Carlos Leong, Marcelino Santos, Isabel Teixeira and Paulo Teixeira

Improved Correction Algorithm for Hot Pixels in Digital Imagers

Glenn Chapman, Rohit Thomas, Rahul Thomas, Israel Koren and Zahava Koren

Diagnosis of segment delay defects with current sensing

Wisam Aljubouri, Ahish Somashekar, Themistoklis Haniotakis and Spyros Tragoudas

12:30- 2:00 Lunch Break

2:00- 3:20 Session 7 - Analysis and Synthesis of resilient systems

Spyros Tragoudas, Southern Illinois University

A Scheduling Algorithm in Datapath Synthesis for Long Duration Transient Fault Tolerance

Tsuyoshi Iwagaki, Tatsuya Nakaso, Ryoko Ohkubo, Hideyuki Ichihara and Tomoo Inoue

Artificial Intelligence Based Task Mapping and Pipelined Scheduling for Checkpointing on Real Time Systems with Imperfect Fault Detection

Anup Das, Akash Kumar and Bharadwaj Veeravalli

A Probabilistic Analysis of Resilient Reconfigurable Designs

Alirad Malek, Stavros Tzilis, Danish Anis Khan, Ioannis Sourdis, Georgios Smaragdos and Christos Strydis

Domino Effect Protection on Dataflow Error Detection and Recovery

Tiago A. O. Alves, Leandro A. J. Marzulo, Sandip Kundu and Felipe M. G. França

3:20 - 3:50 Coffee Break & Poster Session II

3:50 - 5:30 Session 8 - Fault tolerance in FPGA devices

Sandip Kundu, University of Massachusetts, Amherst

Decreasing FIT with Diverse Triple Modular Redundancy in SRAM-based FPGAs

Lucas Antunes Tambara, Fernanda Kastensmidt, Paolo Rech and Christopher Frost

A Fault Injection Methodology and Infrastructure for Fast Single Event Upsets Emulation on Xilinx SRAM-based FPGAs

Stefano Di Carlo, Paolo Prinetto, Daniele Rolfo and Pascal Trotta

Design and implementation of a Self-Healing Processor on SRAM-based FPGAs

Alexandros Vavousis, Mihalis Psarakis, Cristiana Bolchini and Antonio Miele

Aging Analysis for Recycled FPGA Detection

Halit Dogan, Domenic Forte and Mark Tehranipoor

Analytic Reliability Evaluation for Fault-tolerant Circuit Structures on FPGAs

Jahanzeb Anwer and Marco Platzner

5:30 - 6:30 DFT TPC meeting

Poster session I

Estimating the Effect of Single-event Upsets on Microprocessors

Cristian Constantinescu, Srini Krishnamoorthy and Tuyen Nguyen

Unifying Scan Compression

Swapnil Bahl, Shray Khullar, Shreyans Rungta, Rohit Kapur, Anshuman Chandra, Salvatore Talluto, Pramod Notiyath and Ajay Rajagopalan

Exploiting Intel TSX for Fault-Tolerant Execution in Safety-Critical Systems

Florian Haas, Sebastian Weis, Theo Ungerer and Stefan Metzlaff

Exploiting Dynamic Partial Reconfiguration for On-Line On-Demand Testing of Permanent Faults in Reconfigurable Systems

Domenico Sorrenti, Dario Cozzi, Sebastian Korf, Luca Cassano, Jens Hagemeyer, Mario Porrmann and Cinzia Bernardeschi

GPGPUs ECC Efficiency and Efficacy

Daniel Alfonso Gonçalves De Oliveira, Paolo Rech, Laércio L. Pilla, Philippe Navaux and Luigi Carro

A Runtime Manager for Gracefully Degrading SoCs

Stavros Tzilis and Ioannis Sourdis

A Built-In Calibration System with A Reduced FFT Engine for Linearity Optimization of Low Power LNA

Yongsuk Choi, Chun-Hsiang Chang, In-Seok Jung, Marvin Onabajo and Yong-Bin Kim

A Data Recomputation Approach for Reliability Improvement of Scratchpad Memory in Embedded Systems

Hossein Sayadi, Hamed Farbeh, Amir Mahdi Hosseini Monazzah and Seyed Ghassem Miremadi

Shortest Path Reduction in a Class of Uniform Fault Tolerant Networks

Prashant Joshi and Said Hamdioui

SAM: A Comprehensive Mechanism for Accessing Embedded Sensors in Modern SoCs

Miao He and Mohammad Tehranipoor

Poster session II

Machine Learning-based Techniques for Board-level Incremental Functional Diagnosis: a Comparative Analysis

Cristiana Bolchini and Luca Cassano

CONOOPS: A Heuristic Path Selection Method for Small Delay Defects Test

Paniz Foroutan, Mehdi Kamal and Zainalabedin Navabi

Towards an Adaptable bit-width NMR Voter for Multiple Error Masking

Thiago Berticelli Lo, Fernanda Lima Kastensmidt and Antonio Carlos Beck

Automated Formal Approach for Debugging Dividers Using Dynamic Specification

Mohammad-Hashem Haghbayan, Bijan Alizadeh, Amir-Mohammad Rahmani, Pasi Liljeberg and Hannu Tenhunen

Energy-Efficient Concurrent Testing Approach for Many-Core Systems in the Dark Silicon Age

Mohammad-Hashem Haghbayan, Amir-Mohammad Rahmani, Pasi Liljeberg, Juha Plosila and Hannu Tenhunen

A 12-bit 32MS/s SAR ADC Using Built-in Self Calibration Technique To Minimize Capacitor Mismatch

In-Seok Jung and Yong-Bin Kim

Fault Injection in the Process Descriptor of a Unix-based Operating System

Alejandro Velasco, Bartolomeo Montrucchio and Maurizio Rebaudengo

An Instance-based SER Analysis in the Presence of PVTA Variations

Bahar Farahani and Saeed Safari

Preemptive Parallel IJTAG Testing with Reconfigurable Infrastructure

Shahrzad Keshavarz, Amirreza Nekooei and Zainalabedin Navabi

On the in-field functional testing of decode units in pipelined embedded processors

Paolo Bernardi, Riccardo Cantoro, Lyl Ciganda, Ernesto Sanchez, Matteo Sonza Reorda, Sergio De Luca, Renato Meregalli and Alessandro Sansonetti

It is possible to download the flyer of the program here.

*Expected poster size is the typical 27 in. X 30 in..